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noise

  • Re: Noise Figure of an upconverting mixer under input IF signal

    Hi Bennys, just a couple of random thoughts. I guess that in a TX mixer the IF input is 'small signal' anyways, meaning that its amplitude should be well within the range of linear behavior of the IF port, as to avoid introducing distortion. Under this view, one can make full use of the NF concept...
    Posted to RF Design (Forum) by MicheleA on Sat, Nov 2 2013
  • Re: Addition of noise file in transient analysis

    Hi Andrew I finally have a version of Spectre that can turn noises of the devices off. However, when I turn off the noise of a MOS, it still has noise related to: M.rg, M.rs, M.rb, M.rd and M.rdb. Is there a way to turn these noise off as well? Best Hamid
    Posted to RF Design (Forum) by HamidKhatibi on Thu, May 30 2013
  • Noise sources in PSS analysis

    Hi all, I have a pretty simple doubt. I am using Verilog A based circuit netlist to perform circuit simulation in cadence spectre. I have defined some flicker noise sources in the same netlist. If I simulated a simple differential amplifier, I can get the inut referred noise through noise analysis. Now...
    Posted to Custom IC Design (Forum) by OneNewBoy on Tue, May 14 2013
  • transient noise spectre

    Hi all. In transient analysis there is an option for taking into account noise. Which noise components for a MOSFET are being taken into account (ie channel thermal, 1/f etc) or this is model dependent (ie BSIM4 noise parameters supplied). What exactly noise contibution is supposed to do? For example...
    Posted to Custom IC Design (Forum) by soathana on Thu, Oct 18 2012
  • Transient Noise Analysis for clocked circuit and % of contribution of each components at arbitrary time

    Hi All, I want to perform noise analysis for my clocked comparator where the input voltages (inp,inn) vary from cycle to cycle. As a result the conditions of the input MOSFETs change. Therefore the noise contribution also changes as it depends on the saturation level (region of operation) and temperature...
    Posted to Custom IC Design (Forum) by Apolama on Thu, Sep 20 2012
  • cmos mixer

    Hi In general, can we use one mixer circuit as down-conversion mixer as well as up-conversion mixer?
    Posted to RF Design (Forum) by RFDESIGN 2008 on Wed, Apr 18 2012
  • Jitter from pnoise simulation

    I'm desinnig a Time to digital converter and I would like to simulate the jitter of a driven buffer having a rising time of 350 ps. In my schematic, the buffer is driven by vpulse (ideal CLK @ 2 MHz) and I would like to simulate his output jitter. My setting of pss simulation is as follow: Beat frequency...
    Posted to RF Design (Forum) by moez on Fri, Mar 9 2012
  • Why is the Noise Factor that I've counted inconsistent with the result of Pnoise?

    Hi everyone, I've simulated the noise factor of Mixer ne600p in rfExamples library with PSS+Pnoise. With the Noise Summary printed, I calculated the Noise Factor, which is (total noise at output - load noise at output)/(source noise at output), then Noise Figure can be abtained with 10*lg(Noise Factor...
    Posted to RF Design (Forum) by xxgeneral on Thu, Feb 16 2012
  • Cadence noise aware PLL design flow: have lock problem

    Hi All, It is a bit long story. I will try my best to explain it clear. Thanks for your patience to read it through and give me some feedback. Recently I tried to follow Cadence noise-aware PLL design flow (PLL Macro Model Wizard) to verify my design. (We got the PLL_workshop from Cadence already) I...
    Posted to RF Design (Forum) by lunren on Mon, Feb 6 2012
  • Q&A: Jim McCanny Discusses Altos Design and Fast IP Characterization

    In May 2011 Cadence announced the acquisition of Altos Design Automation , a provider of ultra-fast characterization tools that model timing, noise, power, and process variations for "foundation" IP (standard cells, I/Os, memories). In this interview Jim McCanny, co-founder and former CEO of...
    Posted to Industry Insights (Weblog) by rgoering on Tue, Jul 5 2011
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