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noise analysis

  • CDR for USB 3.0 PHY

    Sir, I am modeling a Dual loop CDR for USB 3.0 PHY. As per jitter budgeting of USB 3.0, it specifies a deterministic jitter of 143pSec and random jitter of 4.03pSec. As I was trying to model random jitter using Verilog A function $dist_normal (seed, mean, sd) with mean=0 and sd=4.03p and similarly deterministic...
    Posted to Custom IC Design (Forum) by Jithin on Tue, May 20 2014
  • Transient Simulation 1/f noise

    Hello, I have a simple question: when running transient analysis, is it possible to include 1/f noise in the signal output? I thought that it was only possible using the non-transient noise analysis, but I ran across this on this site, which made me actually sign up and post this question: Pedro, To...
    Posted to Custom IC Design (Forum) by kangjh7 on Thu, Feb 20 2014
  • How can I simulate 'PLL Noise PSD' ?

    I'm fresh designer for PLL. I want to simulate 'PLL Noise PSD' on transient simulation. I had used Analog design environment -> results -> direct plot -> main form. but I couldn't see funtion of 'PLL Noise PSD'. If anybody knows how to simulate 'PLL noise PSD'...
    Posted to Custom IC Design (Forum) by SangKiLEE on Tue, Jul 23 2013
  • Noise sources in PSS analysis

    Hi all, I have a pretty simple doubt. I am using Verilog A based circuit netlist to perform circuit simulation in cadence spectre. I have defined some flicker noise sources in the same netlist. If I simulated a simple differential amplifier, I can get the inut referred noise through noise analysis. Now...
    Posted to Custom IC Design (Forum) by OneNewBoy on Tue, May 14 2013
  • Pnoise analysis

    Hi, I have been designing a PLL which gives an output frequency in the range (400-500)MHz to the reference input frequency of (20-25)MHz.So for doing the pnoise analysis I have added the PSS as well as Pnoise analysis I have made the following as setup for the analysis for a frequency of 500MHz. I have...
    Posted to Custom IC Design (Forum) by Jithin on Sun, Mar 3 2013
  • New Book: Analog Design and Simulation Using OrCAD Capture and PSpice

    Thousands of engineers worldwide use OrCAD Capture for PCB schematic entry and PSpice for circuit simulation. These popular products, both provided by Cadence, deserve a good "how to" book -- and now they have one. It's titled " Analog Design and Simulation Using OrCAD Capture and...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Feb 20 2013
  • noise analysis

    Hello, After running noise analysis, printed noise summary. I couldnt understand te Param info from the summary. What is fn, id, rs etc stands for? Is the total input referred noise = total summarised noise/gain^2 ?
    Posted to Custom IC Design (Forum) by surreyian on Fri, Nov 23 2012
  • Five-Minute Tutorial: Avoid SI Problems With Better Pin Placement In Encounter Digital Implementation (EDI)

    I know we're over halfway through January already (where does the time go?), but Happy New Year everyone! I hope 2012 is a good one for your business and your chip designs, and let's hope the Mayans just ran out of ink when they were finishing the calendar for this year. Today I'd like to...
    Posted to Digital Implementation (Weblog) by Kari on Wed, Jan 18 2012
  • How thermal noise of MOS can be made zero in spectre noise simulation(BSIM 4.6 Model)

    I want to analysis contribution of flicker & thermal noise of complex circuit using spectre simulator separately. Also like to distinguish effect of each MOS contribution to whole circuit noise. Till now I succeed in nulling the effect of flicker noise by making its flag parameters to zero in model...
    Posted to Custom IC Design (Forum) by Ashvink on Thu, Nov 10 2011
  • Tortoise Versus Hare … or How to Improve Your Time to Tapeout Using In-Design Signoff

    Now that Wei Lii Tan has helped you with your New Year’s resolution to “create a chip that is so compelling …” in his previous blog , I would like to help you understand how Cadence is using our signoff qualified engines during the design implementation flow to reduce your time...
    Posted to Digital Implementation (Weblog) by PeteMc on Wed, Feb 23 2011
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