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  • Internal error with topology.c

    Hi, When I try to run a Spectre dc and trans simulation with my 8-bit-adder circuit, have an internal error stopping the simulation. I get the following messages in the spectre log window: 1) the usual "unable to compile ahdlcmi module library" message (which has not stopped my simulations...
    Posted to Custom IC Design (Forum) by CPete on Thu, Jun 2 2011
  • Exporting files

    Hello, Is it possible to export my spectre netlist file generated from my schematic into another environment so that I could use it as an input file for matlab and visual c++? Thx!
    Posted to Custom IC Design (Forum) by EveBell on Wed, Apr 27 2011
  • Encounter Netlist files

    Hello! If I have a transistor level schematic and my simulations show that my circuit is working correctly in virtuoso, how can I generate the verilog netlist and source code to be imported/included for Encounter to design the layout? Thanks in advance!
    Posted to Custom IC Design (Forum) by EveBell on Tue, Mar 29 2011
  • mentor netlist problems at upgrade orcad 10.5 to 16.3

    hi, recently I upgrade my orcad from version 10.5 to 16.3. I load my schematic that I draw in version 10.5 in version 16.3. The problem is when I create Mentor netlist I get something like this: net name at 10.5 version: N27490403 when I create netlist at 16.3 version I get: N27490403_digital , when...
    Posted to PCB Design (Forum) by alon123 on Thu, Feb 17 2011
  • My cadence orcad does't creat a netlist versions 16.3

    Hi everyone! new user of orcad i want to try to creat a board but i have a problem. My problem is that when i want to creat a netlist, nothing happend. Explanation: I creat a design on orcad (simple like rc circuit -> no rules problems and all components have their footprints) I select my project...
    Posted to PCB Design (Forum) by awawa on Sun, Jan 30 2011
  • Monte Carlo simulation in Ocean XL for a text-only netlist

    Hi, I have a netlist and I want to run Monte Carlo simulation. It looks like I need to use ADE XL / OCEAN XL to be able to run Monte Carlo simulation. I generated a script from ADE XL to use as a template and then changed the design command to point to the netlist as follows: design( "netlist"...
    Posted to Custom IC Design (Forum) by Soner on Tue, Apr 27 2010
  • How to make AMS Netlister evaluate pcells

    Hi, I have built a schematic pcell which instantiates different cells according to a parameter. The AMS Netlister does not generate and include different instances per parameter-set in the netlist. If the generated pcell is placed several times with different parameters in a testbench, the normal spectre...
    Posted to Custom IC Design (Forum) by Marode on Wed, Apr 21 2010
  • CIW > File > Import > Verilog... fails to create schematics (portOrder property?)

    Hello I try importing the final verilog (.v) file generated by SoC encounter so I can do LVS for a mixed signal design, but ihdl.exe doesn't generate schematics. The beginning of the log file says (scgp is the digital library name in icfb): @(#)$CDS: ihdl.exe version 5.1.0 12/16/2007 23:32 (cicln04...
    Posted to Custom IC Design (Forum) by skylerweaver on Fri, Feb 12 2010
  • Import spectre netlist

    Hello all, I have to look for real differences of subcircuits in two spectre netlists. It should be the same circuit, but the names of the nets and instances seemes to be compleetly different. My idea is to cut out the parts of the subcircuits definition, import them to a cell (IC5.141) and use the LVS...
    Posted to Custom IC Design (Forum) by Bernd das Brot on Fri, Jan 8 2010
  • Using OA for netlisting

    Hello, I want to use OpenAccess to do my own netlisting. Accessing connectivity data is no problem. Is there a way to access CDF information like attribute mapping, port sequencing and model type ? Regards
    Posted to Custom IC Design (Forum) by 1heinz on Wed, Dec 16 2009
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