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net names

  • OSS netlisting inherited gnd problem

    Dear all, we are having a strange issue when netlising our design with the OSS netlister (via runams command-line). Some of the inherited grounds nets are being strangely netliested. For instance, an inherited net that should be netlisted as \vss! ; is being netlisted as \vss_vss! ; that is, its name...
    Posted to Custom IC Design (Forum) by freitas on Thu, Jul 24 2014
  • OrCAD16.6 DRC check problem: "Net has two or more aliases"

    Hi, I have used net names of my power symbols for various pins. Running DRC I see below messages. How can I get rid of such messaes? INFO(ORCAP-2212): Check Power Ground Mismatch QUESTION(ORCAP-1589): Net has two or more aliases - possible short? U18,PVIN PVIN DDR1V8 SCHEMATIC1, 05-DDR2 & GP Flash...
    Posted to PCB Design (Forum) by Hossein1357 on Mon, Jul 14 2014
  • Driving an internal node several heirarchical layers down...

    All, First, an apology. I am new to ADE XL and spectre, coming from hspice and MICA, so if I am asking a really obvious question, please pardon my ignorance. However, in my defence, this is stumping the local ADE XL expert. I have tried various searches of the forums and google without luck. So here...
    Posted to Custom IC Design (Forum) by deklein on Fri, Mar 14 2014
  • Assura, LVS net mismatch but net doesn't exist

    Hi. The messages given to me by Assura use names of devices and nets that I didn't assign. I assume that they are assigned by Assura and that there's a way to search for these nets but I haven't found it. Example names include nets: avC3, avC5. Example devices: avD20_1. Zooming in and/or...
    Posted to Functional Verification (Forum) by TSmilkstein on Tue, Oct 15 2013
  • Layout pin problem: net name distributes via transistor

    Hi, I am facing a problem in the layout. I designed a DRC free inverter using the gpdk90nm package from pdk.cadence. The final step of placing pins in the circuit invokes net connection errors. When the Out pin of the inverter is placed on the layout, the metal of vdd (not yet assigned) and gnd (not...
    Posted to Custom IC Design (Forum) by jeffreyprin on Fri, Sep 20 2013
  • Line to Shape Spacing DRC on Every Trace

    Hello, I am just starting out with OrCAD 16.5 and I had a few questions. 1. I have imported a design from Capture but in connecting the traces I have a "Line to Shape Spacing" DRC at pretty much every 45* angle junction. It says "constraint value 5mil, actual value 0mil." It's...
    Posted to PCB Design (Forum) by Grue42 on Tue, Oct 23 2012
  • TestPrep in OrCAD PCB Editor

    Ahoy there, I'm using OrCAD PCB Editor to create ICT testpoint. I'm trying to create a report to print net name with its associate testpoint so I can see which nets have testpont and which hasn't. How can I mark nets that already have testpoint in the DSN, so when I run testprep with "Add...
    Posted to PCB Design (Forum) by Alfandari on Wed, Apr 13 2011
  • How to create an ipcd356 netlist with greater than 9999 nets ?

    Hi All: We have a midplane with 10,460+ nets, how do we output an ipcd356 netlist with unique net names ? Thanks, Les
    Posted to PCB Design (Forum) by Les Wong on Tue, Sep 28 2010
  • Assigning a Net to an Unassigned Shape

    I am using Allegro PCB Editor 16.2. I have a symbol (dra file) that has 8 top-layer shapes in it. These shapes are not connected to eachother. Within each shape, I placed a pin which I would like to be electrically connected to its respective net and the shape to be connected to the pin's net (in...
    Posted to PCB Design (Forum) by melview1 on Mon, Dec 14 2009
  • How To Find 1 Unrouted Net?

    I am using OrCAD PCB Editor v16.2 and I have a design that has 1 unrouted net out of 366 nets. I can't find where this unrouted net is. I started by looking for the rats nest, but it doesn't show up. I assume it is a very small disconnect that is difficult to find. Does anyone know a way to find...
    Posted to PCB Design (Forum) by melview1 on Wed, Jul 22 2009
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