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ncsim

  • How to probe VHDL function variables in ncsim?

    Hi, I need to view the variables used inside a function in simvision waveform viewer. How to add a probe to view these variables in the viewer? Thanks, Venkat
    Posted to Functional Verification (Forum) by venkub on Wed, Jun 12 2013
  • TCL based assertion for connectivity check

    Hi, I am using ncsim and i wish to check connectivity between two nets in RTL/netlist using tcl. I remember there being someway where using tcl input file i could specify two nets which could be tested for connectivity. ex: -src net1 -dst net2 on a change of net1 check net2 value is equal to net1 value...
    Posted to Functional Verification (Forum) by harsharaj on Fri, Mar 8 2013
  • Re: forcing the creation of a vcd file

    Hi Stephen, Thanks for the reply. I strictly need it to be in VCD format as I am passing this file to analog team so that they can use is to see if there is any problem in the signal change and in the signal itself. Also we use it in the tester to test the chip. If there is any way around to probe the...
    Posted to Functional Verification (Forum) by Sumeet Shresth on Mon, Nov 26 2012
  • Re: forcing the creation of a vcd file

    Hi Stephen, I am trying to create the VCD for the system verilog varible being defined as struct using the following command: probe -create -vcd bench.ydec_i -depth all but I am facing the issue showing the following error: ncsim: *E,DBOBBD: Cannot create VCD probe for bench.ydec_i. I am using the simvision...
    Posted to Functional Verification (Forum) by Sumeet Shresth on Sun, Nov 25 2012
  • Internal error during elabration phase

    Hi, I am facing the below error when i tried to simulate a simple verilog environment,is this the tool setup issue w.r.t my source file or something other,please help me out. Writing initial simulation snapshot: worklib.tb_counter:v ncsim: *F,INTERR: INTERNAL ERROR Observed simulation time : 0 FS + 0...
    Posted to Functional Verification (Forum) by mdkaleem on Tue, Sep 4 2012
  • about nc_spencman stop

    hi all I have a one question. I do simulate the ncsim with specman. I saw the stop the message " User defined signal 2 " what does mean " User defined signal 2 " ? I don't know what is problem. plz. give me the solution ----------------- stop message ----------------- nc_specman...
    Posted to Functional Verification (Forum) by flicker123 on Tue, Dec 6 2011
  • ncsim without any optimization

    Hi, I want to run my behavioral model using ncsim without any optimization. I look at different option like -linedebug , -access +rwc but none will stop all the optimization like modelsim does with -novopt. Is there any equivalent option is NCSIM? I want to do this because my simulation is giving...
    Posted to Functional Verification (Forum) by beatsonline on Fri, Nov 25 2011
  • vhpi start-of-restart callback

    I'm running a vhpi C++ application. I'm having difficulty getting ncsim to call my start-of-restart function after a restart. Here's my sequence: 1) Start simulation A. I pass the -loadvhpi option to ncsim to load my C++ dlm. 2) Save a snapshot. My vhpi app saves a C++ start-of-restart callback...
    Posted to Functional Verification (Forum) by RonCash on Sun, Jan 16 2011
  • WARN_GLITCH

    Hi All, I am running my e-environment with VHDL testbench and NCSim... while compiling everything is fine.. Till elaboration phase i am not seeing any issue. As soon as i am doing the "run" command in simulator window specman is crashing because of FATAL error (segmentation violation). If i...
    Posted to Functional Verification (Forum) by Ravisinha on Thu, Oct 28 2010
  • end-of-test

    Hi All, I am running one testcase in which i am waiting for power-on-reset to be over and then doing some sequence. In the pre_body i have raised objection and in post_body i have dropped the objection. ISSUE : In the testcase as soon as reset is getting over in the next clock edge i am getting this...
    Posted to Functional Verification (Forum) by Ravisinha on Tue, Oct 19 2010
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