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ncsim timingchecks X states

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  • Timing checks in ncsim

    HI! I am new to using ncsim and all so please excuse for simplistic questions, so anyways I want to simulate a state machine made up of DFFs (with no reset) and some logic gates. When I try to simluate the design electronically everything works fine but if use verilog descriptions of standard library...
    Posted to Functional Verification (Forum) by MTP3 on Wed, May 16 2012
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