Home > Community > Tags > ncsim timingchecks X states
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

ncsim timingchecks X states

Sorry, but there are no more tags available to filter with.
  • Timing checks in ncsim

    HI! I am new to using ncsim and all so please excuse for simplistic questions, so anyways I want to simulate a state machine made up of DFFs (with no reset) and some logic gates. When I try to simluate the design electronically everything works fine but if use verilog descriptions of standard library...
    Posted to Functional Verification (Forum) by MTP3 on Wed, May 16 2012
Page 1 of 1 (1 items)