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nanoroute encounter routing

NanoRoute doesn't route multi height design

Hello, as a test case I have a mixed design with 4 rows only. 3 standard core cell rows and 1 second row, that has a multiple of standard cell row height & pitch. Site definition is done properly. The design contains 2 cells only, one per each row. I created the floorplan, defined the globalNetConnect...

Posted to Digital Implementation (Forum) by scudex on Wed, Feb 6 2013
Nanoroute Problems (Can we do "routeDesign -globalDetail" Twice?)

Hi all, I was doing PnR these two days and found a very strange problem. The command I used is listed as follows: setNanoRouteMode -quiet -drouteUseMultiCutViaEffort medium setNanoRouteMode -quiet -routeInsertAntennaDiode true setNanoRouteMode -quiet -routeWithSiDriven true setNanoRouteMode -quiet -routeWithTimingDriven...

Posted to Digital Implementation (Forum) by ck881256 on Sun, Oct 21 2012
RDL Layer information

Dear sir, How to dump the RDL layer route information, while excluding all other routing layers information in Cadence 9.1. I need to load that data into new design, where it has same package bump and pad structure. Regards Lohith

Posted to Digital Implementation (Forum) by lohith21 on Fri, Apr 29 2011
RULE LEF_DEFAULT definition for Abstract Generator/Encounter/NanoRoute

I am using Cadence Abstract Generator to create abstract cell views for a standard cell library. In the Verify Step, I keep getting the following error: Encounter: (NRDB-158) There is no default via from LAYER MET1 to LAYER MET2 in RULE LEF_DEFAULT. I do not know how or where to define this RULE LEF_DEFAULT...

Posted to Custom IC Design (Forum) by eklikeroomys on Tue, Mar 15 2011
Power Net Extraction Problem in Abstract Generator

Halo, I am creating abstract cell views for a digital standard cell library using Cadence Abstract Generator.I have the following problem: In the Extract Step, I set the tool up to extract signal and power nets and to create pins on metal 1 so that my abstract view will keep its connectivity. The extract...

Posted to Custom IC Design (Forum) by eklikeroomys on Mon, Mar 14 2011
Re: Can Nanoroute constrain one direction in each routing layer?

To force sensitivity to 1 Demintional Lithography by layer you can set this Litho option, f t t t means it is false for M1 and true for the rest. This option is very resrtictive and may require other work on the library and vias if this is your intent. setNanoRouteMode -drouteMinimizeLithoEffectOnLayer...

Posted to Digital Implementation (Forum) by jbillups on Sat, Mar 5 2011
To avoid overlap of metals in different layers

Hi, Can any body tell me if there is any option to route a net without overlapping with metals in different layers. Thanks suraj

Posted to Digital Implementation (Forum) by surajece01 on Tue, Oct 19 2010
Nanoroute seems not to connect IO Pad pins to nets

The problem I have is stated in the subject. I tracked this through a number of warnings at differnet phases in the flow. 1) The first trial route during pre-cts optimization issues the following warning: **WARN: (ENCTR-2325): 42 nets connect a pad term to a fterm without geometry and will not be routed...

Posted to Digital Implementation (Forum) by kasyab on Thu, Oct 14 2010
How to Match Routing wire length?

Hi, I have a 8Bit Data path, each path has equal number of buffers. The buffers are placed at equal distance, now when i route the signals, all the signals should have equal wire length. The Signal in the same path and the signals in the other 8bit paths should have equal wire length after routing ....

Posted to Digital Implementation (Forum) by Sundarsan on Mon, Jul 5 2010
Nanoroute problem

I've a strange problem here, I'm using First Encounter to layout a digital design (about 300K standard cells design), targeting IBM 0.13u technology. What happens is after placement and Clock tree synthesis I use Nanoroute engine for routing, and then use timing optimization to meet time constraints...

Posted to Digital Implementation (Forum) by amrzahir on Mon, Oct 26 2009

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nanoroute encounter routing

NanoRoute doesn't route multi height design

Nanoroute Problems (Can we do "routeDesign -globalDetail" Twice?)

RDL Layer information

RULE LEF_DEFAULT definition for Abstract Generator/Encounter/NanoRoute

Power Net Extraction Problem in Abstract Generator

Re: Can Nanoroute constrain one direction in each routing layer?

To avoid overlap of metals in different layers

Nanoroute seems not to connect IO Pad pins to nets

How to Match Routing wire length?

Nanoroute problem