Home > Community > Tags > naming style RC/rtl compiler
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

naming style RC,rtl compiler

  • How to blast a selected busse in RC ?

    I have defined in my design a bus wire. In the corresponding verilog it is seen as : wire [3:0]MyBusWire How can I blast this wire in RC ? The nets will become : wire MyBusWire_0, MyBusWire_1, MyBusWire_2, MyBusWire_3; Of course I want to keep all my other busses unblasted ! Patrick.
    Posted to Logic Design (Forum) by PatBoug on Wed, Aug 18 2010
Page 1 of 1 (1 items)