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naming style RC

  • unwanted "\" in netlist

    Hi: I am using RC12 and I found after the synthesized netlist is written out, some net names contains "\", ex: \plus_77_14[23] I use [find / -net \\plus77_14*] and I cannot get this net since RC doesn't really take "\" as part of the net name internally. I can only find this net...
    Posted to Logic Design (Forum) by tompy on Tue, Sep 3 2013
  • How to blast a selected busse in RC ?

    I have defined in my design a bus wire. In the corresponding verilog it is seen as : wire [3:0]MyBusWire How can I blast this wire in RC ? The nets will become : wire MyBusWire_0, MyBusWire_1, MyBusWire_2, MyBusWire_3; Of course I want to keep all my other busses unblasted ! Patrick.
    Posted to Logic Design (Forum) by PatBoug on Wed, Aug 18 2010
  • naming style for generate statement in RTL

    I have a generate statement in my verilog RTL. generate for(g=0; g<num_reg; g=g+1) begin wb_reg #(._address(reg_addr[g*_width+:_width]), ._default(reg_default[g*_width+:_width]), ._bit_mask(reg_bit_mask[g*_width+:_width]), ._autoclr(reg_autoclr[g*_width+:_width])) wb_regs ( .CLK_I(CLK_I), .RST_N_I...
    Posted to Logic Design (Forum) by diablo on Wed, Nov 25 2009
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