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nVidia

  • System Development Suite Is Key Draw at Embedded Systems Conference (ESC)

    For press and analysts, the Cadence booth was the place to be at the Embedded Systems Conference (ESC) in San Jose, California, at 3:00 p.m. Tuesday May 3. That's when the shroud came off the covered booth and Cadence officially unveiled the System Development Suite , a new set of concurrent, connected...
    Posted to Industry Insights (Weblog) by rgoering on Wed, May 4 2011
  • NVidia Engineer Cites HW/SW Integration Challenges

    One of the biggest challenges facing NVidia is the verification of software applications in the context of overall system designs, according to Narendra Konda, director of hardware engineering at NVidia. Konda was a speaker at the Cadence EDA360 introductory event at the San Jose Tech Museum April 27...
    Posted to Industry Insights (Weblog) by rgoering on Wed, May 5 2010
  • CES Provides Wake-Up Call for EDA

    Since consumer electronics is the primary driver for IC and systems design, what happens at the Consumer Electronics Show (CES) should interest the EDA community. Any trends in new consumer devices will point the way to design challenges EDA tools will have to solve. From looking at blogs and media coverage...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Jan 11 2010
  • From Cadence Earning Call This Week

    In system development, we have focused on two key customer challenges. First, we are increasing their productivity by elevating design and verification to the next level of abstraction. This quarter, we announced the industry’s first transaction-level modeling, or TLM, design and verification flow...
    Posted to System Design and Verification (Weblog) by Ran Avinun on Mon, Nov 2 2009
  • Expect the Unexpected - Using MSV Beyond MSV

    I was just reading Rich Owen's post, "What I am Thankful for - The Geek Version" , and I cannot agree more on the creative and sometimes utterly crazy uses of technology that users find. More often than one would guess we ran into users who are trying some truly unexpected uses of technology...
    Posted to Logic Design (Weblog) by grasshopper on Mon, Dec 1 2008
  • SPB 16.2 release - Constraint Driven HDI PCB Design Flow

    Today's SPB 16.2 release is significant for the Cadence Allegro and OrCAD families of products, but more importantly, I think it brings a lot of new functionality for PCB designers. I will be talking about the improvements in this release over a few blog posts in coming days and weeks. First and...
    Posted to PCB Design (Weblog) by hemant on Mon, Aug 18 2008
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