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Vigyan Singhal
CDNLive High-Performance Track: Do You Have What it Takes to Get Your High-Performance SoC to Market?
Implementing SoCs with embedded processors at advanced nodes has become increasingly difficult. This is due to the complexity of the design functionality as well as the low power and increased performance requirements driven by a plethora of end-user applications in modern hand-held devices. Path-breaking...
Posted to
Digital Implementation
(Weblog)
by
Vasu Madabushi
on Sun, Mar 10 2013
DVCon 2013 for Formal and ABV Users
At the upcoming DVCon (in San Jose, CA February 25-28) , Cadence will cover all aspects of our verification technologies and methodologies (full list of Cadence-sponsored events is here ). However, Team Verify would like to alert users of Cadence Incisive formal and multi-engine tools, apps, and assertion...
Posted to
Functional Verification
(Weblog)
by
TeamVerify
on Mon, Feb 11 2013
DesignCon NVIDIA Keynote: Engineers Should Complain About Outdated EDA Tools
If engineers suspect they don't have the best EDA tools for the job, they shouldn't be quiet and complacent - they should be assertive and complain. Promoting that kind of environment is one of seven "rules for methodology investment" presented by Jonah Alben, senior vice president...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Jan 29 2013
Allegro 16.6: Easing PCB Design for Multi-Gigabit/Second Signals
Got a few picoseconds to spare? If you're a PCB designer working with a multi-Gbit/second serial link interface such as PCI Express 3.0 or a DDR memory interface, maybe not. Two new features in the Cadence Allegro 16.6 PCB design solution - announced today (Sept. 25, 2012) at PCB West - aim to help...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Sep 25 2012
Video: Oski Technology’s Courageous "72 hour Verification Challenge" Using Incisive Enterprise Verifier (IEV)
I've seen a lot of intriguing promotions over the years, but at DAC 2012 our partners at Oski Technology tackled a truly unique challenge. To show off their formal verification prowess they took an IP block from NVIDIA sight unseen (actually, on Sunday evening before the DAC they received a spec...
Posted to
Functional Verification
(Weblog)
by
TeamVerify
on Mon, Jun 25 2012
DAC 2012: Users Cite Experiences With Hardware/Software Co-Development
Hardware/software co-development tools such as virtual prototyping, emulation, and FPGA-based prototyping are in use today and are making a difference. That was the message behind a Cadence-sponsored breakfast at the Design Automation Conference ( DAC 2012 ) June 5, where two users described their experiences...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Jun 17 2012
Lessons from CDNLive! India Best Paper -- Property Driven Simulation in IEV
Recently the CDNLive! India 2011 best paper award winner, "Complex IP Verification Methodology Using Property Driven Simulation in IEV," was published in TechOnline India. This is great news for the verification community because the techniques the NVidia authors describe have broad applications...
Posted to
Functional Verification
(Weblog)
by
TeamVerify
on Fri, Apr 13 2012
System Development Suite Is Key Draw at Embedded Systems Conference (ESC)
For press and analysts, the Cadence booth was the place to be at the Embedded Systems Conference (ESC) in San Jose, California, at 3:00 p.m. Tuesday May 3. That's when the shroud came off the covered booth and Cadence officially unveiled the System Development Suite , a new set of concurrent, connected...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, May 4 2011
NVidia Engineer Cites HW/SW Integration Challenges
One of the biggest challenges facing NVidia is the verification of software applications in the context of overall system designs, according to Narendra Konda, director of hardware engineering at NVidia. Konda was a speaker at the Cadence EDA360 introductory event at the San Jose Tech Museum April 27...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, May 5 2010
CES Provides Wake-Up Call for EDA
Since consumer electronics is the primary driver for IC and systems design, what happens at the Consumer Electronics Show (CES) should interest the EDA community. Any trends in new consumer devices will point the way to design challenges EDA tools will have to solve. From looking at blogs and media coverage...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Jan 11 2010
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