Log In
|
Register
|
Resource Library
|
Worldwide
Asia-Pacific
|
China
|
EMEA
|
India
|
Israel
|
Japan
|
Korea
|
Taiwan
|
Global Office Locator
Solutions
Products
Services
Support & Training
Alliances
Community
About Cadence
Solutions:
Design IP
Mixed-Signal
Low-Power
Advanced Node
3D-IC
Enterprise Verification
Hosted Design
System Development Suite
Solutions Home
Products for:
System Design and Verification
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Manufacturability Signoff
More Products
OrCAD Products
Sigrity Technologies
Design IP
Verification IP
IP Catalog
Products A-Z
Products Home
Capabilities and Practices
Methodology Services
Design Services
DFM Services
Educational Services
Programs
SOI Design Hub
Services Home
Support
Support Offerings
Support Process
Cadence Online Support
Software Downloads
Computing Platform Support
University Software Program
Training
Training Options
Training Course Catalogs
Support & Training Home
Programs and Initiatives
System Realization Alliance
Foundry Program
ChipEstimate.com - Chip Planning Portal
Connections Program
Verification Alliance Program
Channel Partner (VARs) Program
Power Forward Initiative
Standards and Languages
PCB Service Bureaus
Industry Memberships
Alliances Home
Communities
Industry Insights Blog
Low Power Blog
Mixed-Signal Design Blog
System Design and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Quicklinks
All Blogs
All Forums
Community Search
CDNLive User Conferences
Community Home
EDA Vision
Visit the EDA360 microsite
News and Events:
Newsroom
Events and Webinars
Resources:
Customer Success
Newsletters
Publications
Multimedia Center
Logos
Company Info:
Investor Relations
Executive Team
Careers
Contact Us
About Cadence Home
Home
>
Community
>
Tags
> multicore
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.
Register
|
Membership benefits
Get email delivery of the Cadence blog (individual posts).
Industry Insights
Low Power
Mixed-Signal Design
System Design
and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Manufacturability Signoff
All Blog Categories
Popular Tags
Allegro
Analog
ARM
cadence
DAC
Digital Implementation
e
EDA360
encounter
ESL
functional verification
Incisive
industry insights
Low power
Mixed-Signal
OVM
PCB
PCB design
Specman
System Design and Verification
SystemC
TLM
UVM
Verification
Virtuoso
Browse All Tags
Email
*
Required Fields
Recipients email
*
(separate multiple addresses with commas)
Your name
*
Your email
*
Message
*
Send yourself a copy
Share
Twitter
Facebook
LinkedIn
Google+
Subscribe
RSS
Cadence RSS Feeds
Cadence Press Releases
System Design and Verification Blog
Functional Verification Blog
Digital Implementation Blog
Custom IC Design Blog
RF Design Blog
PCB Design Blog
IC Packaging and SiP Design Blog
Manufacturability Signoff Blog
All Blogs
System Design and Verification Forum
Functional Verification Forum
Digital Implementation Forum
Custom IC Design Forum
Custom IC SKILL Forum
Logic Design Forum
RF Design Forum
PCB Design Forum
PCB SKILL Forum
IC Packaging and SiP Design Forum
Manufacturability Signoff Forum
Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.
Contact Us
Cadence Contacts
Community Relations
Customer Support
Employment
Investor Relations
Media Relations
Training
Global Office Locator
Find Offices worldwide
»
Sales Inquiry
Request for Product information
»
Cadence Channel Partners
»
Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234
*
Required Fields
First Name
*
Last Name
*
Email
*
Company / Institution
*
Comments:
*
Send Yourself A Copy
multicore
Amdahl’s Law
applications
apps
APS
architect
architectural
ARM
ARM Techcon
assertion-based verification
Avinun
Bailey
Black
Co-Design
co-development
Cortex-A9
Cortex-M3
co-verification
Custom IC Design
DAC
DAC 2011
DAC 2012
DAC keynote
Dare
debugging
Dennard scaling
Design Automation Conference
digital implementation
EDA
EDA360
EDI
EDI 8.1
EDP
EE Times
elaboration
Electronic Design Processes
embedded
embedded software
Encounter
fast models
formal
Freescale
Friedrich
Functional Verification
gate-level simulation
GPU
Groeneveld
hardware/software
Heaney
IES
IEV
IFV
Incisive
Incisive Enterprise Simulator
Industry Insights
Intel
IP
multi-core
parallelism
RTL simulation
scaling
Si2
Silicon Realization
simulation
simulation speed
simulator performance
SMP
SoC
SoC conference
SoCs
software
space-based router
spectre
Spice 2.0
Spyrou
Standards
Su
System Design and Verification
System Development Suite
SystemC
SystemC analysis
TLM
TLM 2.0
TLM2
TLM-2
uvm
verification
VIP
virtual conference
virtual platform
virtual platforms
virtual prototoyping
virtual prototypes
Virtual System Platform
Virtuoso
vPlan
VSP
white paper
whitepaper
Wind River
yield
DAC 2012 IBM Keynote: Multi-Core Performance Growth Slowing, New Approaches Needed
In the early 2000s we hit a power "wall" and decided to scale it by putting multiple processor cores on a single chip. But the multi-core era is running into limitations, and it's time to start planning for a "new era" in which design innovation will fuel performance growth, according...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Jun 10 2012
Whitepaper: Verification Performance is More Than Raw Simulation Speed
RTL and gate-level simulation have been the workhorses of the IC verification environment for 25 years, and they're orders of magnitude faster than they used to be. But as chip complexity skyrockets and process nodes shrink, a continuous cry arises from verification teams - "make it faster,...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Jan 31 2012
ARM TechCon Paper: Using a Virtual Platform for Multi-Core Software Development
You may have heard that "virtual platforms" enable software development and debugging before system hardware is available. But how do you build them, how do you solve common problems, and how do you debug software and hardware for multi-core systems? These questions and more were answered in...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Nov 21 2011
Freescale DAC Keynote: EDA Support Needed for Multi-Core Embedded Devices
Lisa Su, senior vice president and general manager at Freescale Semiconductors, needs some help from the EDA community. In a dynamic keynote speech at the Design Automation Conference June 7, she set forth a list of hardware and software design tool requirements for the oncoming generation of multi-core...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Jun 8 2011
Panelists: A Reality Check on Hardware/Software Co-Design and Co-Verification
Is hardware/software co-development ready for prime time? Yes, but much remains to be done, according to panelists at the May 12 EE Times System on Chip "Virtual Event." Panelists discussed hardware/software partitioning, benefits of co-design and co-verification, barriers to adoption, what's...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, May 16 2011
Building Open Virtual Platforms - Bridging the Gap of Model Availability
Virtual prototypes promise to enable early software development, shorten system bring-up time, and provide a resulting increase in revenue. One of the key barriers that project teams face when considering use of virtual prototypes is the "missing model syndrome" -- essentially the lack of adequate...
Posted to
System Design and Verification
(Weblog)
by
Steve Brown
on Wed, May 4 2011
What Does Silicon Realization Mean for Verification Engineers?
Last May , I posed a question about what EDA360 means for verification engineers. Yesterday we made an announcement about verification for Silicon Realization that is a big deal. We are delivering a lot of new technology with immediate and high value to verification engineers everywhere. My colleagues...
Posted to
Functional Verification
(Weblog)
by
tomacadence
on Tue, Jan 11 2011
Cadence OpenAccess Development Team: The Inside Story
Many people are unaware that after donating the OpenAccess database to the Silicon Integration Initiative ( Si2 ) in 2002, Cadence has continued to maintain, revise and improve the OpenAccess reference implementation at its own expense. A recent Si2 award brought this contribution to light, and this...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Nov 18 2010
The Amazing Diversity of the SoC Conference
Although I attend a number of conferences and tradeshows each year, most of these are rather EDA-centric. But last week I was in Irvine for the eighth annual International System-on-Chip (SoC) Conference. It is a fairly small event -- more like a workshop in some ways -- with a single track over its...
Posted to
Functional Verification
(Weblog)
by
tomacadence
on Mon, Nov 8 2010
EDA Workshop Debate Erupts Over Parallel Programming
The Electronic Design Processes (EDP) workshop may be a small, technical, IEEE-sponsored event, but that didn't stop a lively debate over the feasibility of parallel processing from erupting last week. The debate comes as EDA vendors, including Cadence, are working hard to port their software to...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Apr 12 2010
Page 1 of 2 (16 items) 1
2
Next >