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multi-language,IES
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webinar
UVM SystemVerilog in a Multi-Language SoC World: UVM-ML Webinar
Every SoC project uses multiple languages. Even if the design itself is purely Verilog RTL, it's likely that you have some PLI-based stimulus. In many cases there are multiple languages in use due to multiple suppliers, globalized teams, multiple abstractions, and more. Integrating e , SystemVerilog...
Posted to
Functional Verification
(Weblog)
by
Adam Sherilog
on Thu, Oct 11 2012
UVM: "Everything that Can be Invented Has Been Invented" Not True!
Much like Charles Duell's famous 1899 quote**, the notion that the Universal Verification Methodology ( UVM ) is the be-all and end-all of verification methodology is an urban legend. The new Advanced Verification Topics book dispells this myth with five topics that describe methodology layers that...
Posted to
Functional Verification
(Weblog)
by
Adam Sherilog
on Thu, Jan 26 2012
Come See How to Connect SystemVerilog and SystemC Using UVM
All pun-tastic references aside, connecting SystemVerilog and SystemC is becoming a commonplace request. In most cases, the request is to do this using UVM as the testbench methodology. One of our resident technical experts, Phu Huynh, will lead a webinar on this subject on October 20. Cadence pioneered...
Posted to
Functional Verification
(Weblog)
by
Adam Sherilog
on Tue, Oct 18 2011
Tips on Using “vhdlsync” With e+Mixed HDL Simulation
[ Team Specman welcomes Principal Support Application Engineer Avi Farjoun to share some important tips on the famous “vhdlsync” switch] As users with mixed VHDL and Verilog environments know, even in this day & age mixed HDL simulation cycle semantics are not very well defined. Even...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Thu, Jun 11 2009
e Running Inside VCS Anniversary Updates?
It's been a year since I heard the first solid report about Synopsys supporting the e language (IEEE 1647-2008) natively inside VCS. (Note a key distinction here: VCS has interfaced with e language and/or Specman-driven testbenches for years -- that's not what I'm referring to. The issue...
Posted to
Functional Verification
(Weblog)
by
jvh3
on Thu, Nov 20 2008
Report from last week's "ClubT" events; preview of next week
As promised, here are some photos last week events, with embedded color commentary. NOTE: there are two additional events next week that will be featuring none other than fellow blogger and Cadence Distinguished Engineer Mike Stellfox: Kista, Sweden on Monday October 6 Bristol, UK on Wednesday October...
Posted to
Functional Verification
(Weblog)
by
jvh3
on Wed, Oct 1 2008
In the EU next week for "ClubT" verification events
I'll be in the EU next week supporting "ClubT" events focused on advanced verification, with previews of new developments in the "Trailblazer" program. If you are based in the EU and are active in verification in any way, chances are you have already received a direct invitation...
Posted to
Functional Verification
(Weblog)
by
jvh3
on Fri, Sep 19 2008
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