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Q&A: Anirudh Devgan Discusses New Cadence Signoff Strategy
Anirudh Devgan is corporate vice president of R&D for Silicon Signoff and Verification, which is part of the Silicon Realization Group at Cadence. Last week (May 20, 2013) Cadence announced the first new product in this space, the Tempus Timing Signoff Solution . Tempus provides up to an order of...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, May 28 2013
Tempus – Parallelized Computation Provides a Breakthrough in Static Timing Analysis
Cadence this week (May 20, 2013) announced the Tempus Timing Signoff Solution , a new static timing analysis and closure tool that offers significant speed and capacity advantages over existing solutions. Tempus promises to accelerate signoff timing closure by a matter of weeks. One factor behind this...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, May 20 2013
DAC 2012 IBM Keynote: Multi-Core Performance Growth Slowing, New Approaches Needed
In the early 2000s we hit a power "wall" and decided to scale it by putting multiple processor cores on a single chip. But the multi-core era is running into limitations, and it's time to start planning for a "new era" in which design innovation will fuel performance growth, according...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Jun 10 2012
In-Circuit Acceleration – A New IC Verification Use Model
Last year Cadence introduced the System Development Suite , a set of four connected hardware/software co-development platforms. Today (May 15, 2012) Cadence is announcing a new release of the System Development Suite that is highlighted by a new verification use model called in-circuit acceleration....
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, May 15 2012
Gentlemen, Start Your Simulation Engines
As we outlined in our recent performance white paper , every verification team has the need for higher performance simulation. Of course, you can expect on-going innovation from Cadence R&D, but there are some things you can do to get more from your engine at any time. The February 23, 2012 webinar...
Posted to
Functional Verification
(Weblog)
by
Adam Sherilog
on Wed, Feb 22 2012
Whitepaper: Verification Performance is More Than Raw Simulation Speed
RTL and gate-level simulation have been the workhorses of the IC verification environment for 25 years, and they're orders of magnitude faster than they used to be. But as chip complexity skyrockets and process nodes shrink, a continuous cry arises from verification teams - "make it faster,...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Jan 31 2012
ARM TechCon Paper: Using a Virtual Platform for Multi-Core Software Development
You may have heard that "virtual platforms" enable software development and debugging before system hardware is available. But how do you build them, how do you solve common problems, and how do you debug software and hardware for multi-core systems? These questions and more were answered in...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Nov 21 2011
Freescale DAC Keynote: EDA Support Needed for Multi-Core Embedded Devices
Lisa Su, senior vice president and general manager at Freescale Semiconductors, needs some help from the EDA community. In a dynamic keynote speech at the Design Automation Conference June 7, she set forth a list of hardware and software design tool requirements for the oncoming generation of multi-core...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Jun 8 2011
Panelists: A Reality Check on Hardware/Software Co-Design and Co-Verification
Is hardware/software co-development ready for prime time? Yes, but much remains to be done, according to panelists at the May 12 EE Times System on Chip "Virtual Event." Panelists discussed hardware/software partitioning, benefits of co-design and co-verification, barriers to adoption, what's...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, May 16 2011
Building Open Virtual Platforms - Bridging the Gap of Model Availability
Virtual prototypes promise to enable early software development, shorten system bring-up time, and provide a resulting increase in revenue. One of the key barriers that project teams face when considering use of virtual prototypes is the "missing model syndrome" -- essentially the lack of adequate...
Posted to
System Design and Verification
(Weblog)
by
Steve Brown
on Wed, May 4 2011
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