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modeling

DAC 2013 -- Kaufman Winner Hu: FinFETs Will Serve Analog Design Very Well

AUSTIN, Texas--The father of the FinFET, who spent a career "attacking the barriers to Moore's Law," says the technology is going to surprise people when it comes to its utility for analog designs. Chenming Hu, TSMC Chair Professor at U.C. Berkeley, in accepting the 2013 EDAC Phil Kaufman...

Posted to The Fuller View (Weblog) by Brian Fuller on Sun, Jun 2 2013
Video: A Unified Modeling Flow for Virtual Platforms and High-Level Synthesis

Can the same SystemC TLM2 models be used in virtual platforms and high-level synthesis? Today the answer is typically "no." However, there is a "middle ground" modeling methodology that can turn this "no" into a "yes," according to Stuart Swan, senior architect...

Posted to Industry Insights (Weblog) by rgoering on Thu, Apr 11 2013
Webinar: Is SystemVerilog the Future of Mixed-Signal Modeling?

Real number modeling (RNM) provides a fast way to run a chip-level simulation with analog values, but support for it in the current SystemVerilog Language Reference Manual (2009 LRM) is very limited. A recently archived webinar shows how the next SystemVerilog LRM (which may be dated 2012 or 2013) offers...

Posted to Industry Insights (Weblog) by rgoering on Thu, Oct 4 2012
DAC 2012 Panel – Can One System Model Serve Everybody?

Can one system model ever serve the needs of system architects, hardware developers, software developers, and verification teams? Probably not, according to panelists at the Design Automation Conference (DAC 2012) June 5. But panelists had some informative perspectives on the various types of models...

Posted to Industry Insights (Weblog) by rgoering on Tue, Jun 5 2012
Is System Modeling the Next EDA Abstraction Level?

According to a recent talk by Frank Schirrmeister, group director of product marketing for the Cadence System and Software Realization Group, the answer is "yes." System modeling is a level of abstraction that's independent from hardware and software implementation. But there are some interesting...

Posted to Industry Insights (Weblog) by rgoering on Sun, Apr 15 2012
Hot Topic Revisited: System-Level Design and a “New Class” of Engineer

Six months ago I wrote a blog post that considered the question, Is System-Level Design Creating a New Class of Engineer? Since then an ongoing discussion in the LinkedIn electronic system level (ESL) design group has added some new perspectives not considered in my original blog post. To quickly recap...

Posted to Industry Insights (Weblog) by rgoering on Thu, Oct 6 2011
Building Open Virtual Platforms - Bridging the Gap of Model Availability

Virtual prototypes promise to enable early software development, shorten system bring-up time, and provide a resulting increase in revenue. One of the key barriers that project teams face when considering use of virtual prototypes is the "missing model syndrome" -- essentially the lack of adequate...

Posted to System Design and Verification (Weblog) by Steve Brown on Wed, May 4 2011
DVCon: Mixed-Signal Designers Cite Verification Challenges and Needs

If you want to know how challenging mixed-signal verification really is, the best thing is to listen to the people in the trenches. A March 3 lunch panel at the DVCon conference, sponsored by Cadence, allowed an attentive audience to do just that. The panel included three users and two vendor representatives...

Posted to Industry Insights (Weblog) by rgoering on Sun, Mar 6 2011
The Increasing Role of SystemC in System Design

Today's post is less technical and a bit more theoretical, but I promise that my next post will be more hands-on. As somebody working on virtual platforms in an EDA company, I regularly spend time talking to firmware and embedded software engineers with many different backgrounds. Every so often...

Posted to System Design and Verification (Weblog) by jasona on Tue, Feb 22 2011
De-Mystifying SystemC: What is TLM?

In my last post I briefly mentioned that when designing hardware with SystemC, you do not need to allocate logic to register boundaries. And I said that was a blog post for another day. The first step is to separate the core functionality of the block from the way it interfaces to the system. So if you...

Posted to System Design and Verification (Weblog) by Jack Erickson on Thu, Feb 3 2011

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modeling

DAC 2013 -- Kaufman Winner Hu: FinFETs Will Serve Analog Design Very Well

Video: A Unified Modeling Flow for Virtual Platforms and High-Level Synthesis

Webinar: Is SystemVerilog the Future of Mixed-Signal Modeling?

DAC 2012 Panel – Can One System Model Serve Everybody?

Is System Modeling the Next EDA Abstraction Level?

Hot Topic Revisited: System-Level Design and a “New Class” of Engineer

Building Open Virtual Platforms - Bridging the Gap of Model Availability

DVCon: Mixed-Signal Designers Cite Verification Challenges and Needs

The Increasing Role of SystemC in System Design

De-Mystifying SystemC: What is TLM?