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CDNLive! 2012 Proceedings – Over 150 User Presentations on Design and Verification
A fantastic resource is available for chip and system designers -- proceedings from five of the CDNLive! Conferences held in 2012. By my count this includes over 150 user-authored presentations given at CDNLive! Silicon Valley (March 12-13), CDNLive! EMEA (May 6-8), CDNLive! Taiwan (July 11), CDNLive...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Jan 9 2013
New Rapid Adoption Kit (RAK) Enables Productive Mixed-Signal, Low Power Structural Verification
All engineers can enhance their mixed-signal low-power structural verification productivity by learning while doing with a PIEA RAK (Power Intent Export Assistant Rapid Adoption Kit). They can verify the mixed-signal chip by a generating macromodel for their analog block automatically, and run it through...
Posted to
Low Power
(Weblog)
by
SumeetAggarwal
on Mon, Dec 10 2012
Cadence at ARM TechCon – Verification IP, 14nm FinFET, Low Power, Mixed Signal, and More
With nine technical paper presentations, six sponsored sessions, demos, and exhibits, Cadence will have a strong presence at ARM TechCon in Santa Clara, California Oct. 30-Nov. 1, 2012. Cadence papers and sessions will cover topics including advanced-node digital, mixed-signal, low power, verification...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Oct 23 2012
Mixed Signals from European Low-Power Designers
Early summer is a good time to visit Europe. I was there for the first couple of weeks in July, before most of Europe disappears on vacation. I spent my time mainly with customers in Germany, Ireland and the UK. It's not the weather that makes it a good time to visit - while it was nice in Germany...
Posted to
Low Power
(Weblog)
by
Pete Hardee
on Wed, Jul 25 2012
Panel: Integrating Low-Power ARM Processors into Mixed-Signal Designs
Mixed-signal chip designs with embedded digital signal processing are becoming more and more commonplace these days. How can you bring low-power processors, such as the ARM Cortex-M0 , into such designs quickly and efficiently? A lunch panel discussion at the recent Design Automation Conference (DAC...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Jun 20 2012
What’s Cool for Low-Power at DAC?
Low-power design promises to be a key theme of the Design Automation Conference once again! At DAC 2012 at San Francisco's Moscone Center next week (June 4-7), if you need to cover design, implementation and verification of this important subject, there's a lot to choose from at Cadence's...
Posted to
Low Power
(Weblog)
by
Pete Hardee
on Wed, May 30 2012
Mixed-Signal Methodology Guide Sets New Directions for SoCs
Nearly all systems-on-chip (SoCs) these days are mixed-signal, with increasingly complex analog/mixed-signal (AMS) IP blocks. Meanwhile, analog blocks increasingly contain digital control logic. Yet analog and digital design are still done in relative isolation, using very different methodologies and...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, May 30 2012
12 Hot EDA Topics – 78 DAC Demo Sessions
Whatever your role in the chip or system design process, there is probably a Cadence demo geared to your interests at the Design Automation Conference ( DAC 2012 ) June 3-7 in San Francisco. Cadence has three demo suites at its booth (#1930) and is running one-hour demos from 10:00 am to 5:00 pm Monday...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, May 24 2012
Managing Inherited Connections with CPF in Virtuoso
Let's assume you are managing a schematic-driven top level design in Virtuoso and you want to import a digital block Verilog netlist into Virtuoso. This is a very common use model in mixed-signal implementation. While the Layout Database is saved in Open Access (OA), the optimized Verilog netlist...
Posted to
Mixed-Signal Design
(Weblog)
by
AndreasLenz
on Wed, May 23 2012
Free DAC Lunches: Custom/Analog Variability, ARM Low Power Processors in Mixed-Signal Designs
There is such a thing as a free lunch - if you're at the 49th Design Automation Conference (DAC) in San Francisco June 3-7. Cadence is sponsoring two lunches at which you can learn about two important technology topics - custom/analog variability, and the use of ARM processors in low-power, mixed...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, May 14 2012
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