Home > Community > Tags > mixed-signal/SoC
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

mixed-signal,SoC

  • CES Provides Wake-Up Call for EDA

    Since consumer electronics is the primary driver for IC and systems design, what happens at the Consumer Electronics Show (CES) should interest the EDA community. Any trends in new consumer devices will point the way to design challenges EDA tools will have to solve. From looking at blogs and media coverage...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Jan 11 2010
  • Panel Question: Should Designers Do Their Own Verification?

    One question that prompted a lively discussion at the recent Cadence Mixed-Signal Design Summit was whether design engineers should do their own verification. This is a particularly good question for analog and mixed-signal design, where the tradition of separate verification teams is not as strong as...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Nov 11 2009
  • User Interview: Running Full Chip Mixed-Signal Simulations

    Running full-chip, mixed-signal simulations with sufficient accuracy and speed is a huge challenge for system-on-chip (SoC) designers. But engineers at SiRF , a provider of GPS chipsets and subsystems, have been able to do so, according to Marcelo Silva, verification engineer. In an interview at the...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Sep 17 2009
Page 2 of 2 (13 items) < Previous 1 2