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mixed-signal verification,VerilogAMS


    I am new to AMS language and design and I am trying to model an oscillator with the following features : a. The oscillator operates at a default freq of say 32Khz, with tuning applicability from 20Khz to 50Khz. b. The oscillator operates in two power domains, one of 3.3v and other of 1.2v. c. When the...
    Posted to Mixed-Signal Design (Forum) by Sayantan55 on Sun, Sep 15 2013
  • Verilog-AMS Bias Current Modelling

    Hi All, I need to model a verilog-ams bias current model. I had coded in this way, I(out) <+ 1uA. In TB i put V(out) <+I(out)/R_LAOD. This worked fine at module level. Does this way of model works when the module connects with a SPICE block where the current is begin sinked. Is this the correct...
    Posted to Mixed-Signal Design (Forum) by shalem7 on Wed, Sep 4 2013
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