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mixed-signal verification,ADE

  • Re: mixed signal simulation

    thanks for your valuable guidance.... sir, in my project i have designed one block in verilog.Now i need to integrate it to the remaining analog blocks. so i generate verilog netlist of the corresponding digital block. But after integrating it with analog block i need to check functional and transistor...
    Posted to Mixed-Signal Design (Forum) by KUMARJAYA on Thu, Jul 17 2014
  • Re: Switched Cap based System Noise Analysis

    Hi Andrew, Previously I gave some incorrect information. My flow is like that 1) Comparator sampling bandgap charge @ 400 Khz 2) Comparator sampling input charge @ 400 Khz but after 1. ( Phase lag ) 2) Caps are connecting disconnecting @ 2 Mhz Best Regards Abhishek
    Posted to Mixed-Signal Design (Forum) by Abhishek D on Mon, Feb 10 2014
  • Re: Switched Cap based System Noise Analysis

    Hi Andrew, Following are the details- 1) Comparator goes to unity feedback and then openloop - 222.22k 2) There are some caps and they either get connected b/w input of comparator and Supply or Input of comparator and ground- 2MHz 3) There is one switched cap BGREF. When comparator goes in unity feedback...
    Posted to Mixed-Signal Design (Forum) by Abhishek D on Mon, Feb 10 2014
  • Re: Switched Cap based System Noise Analysis

    Hi Andrew, Thank you for being always first to answer. I referred your attachment before putting my query. But this says, it takes only one clock. In my system multiple switchings are happening and that too at different rates. Pardon my ignorance if I am not able to understand the material you attached...
    Posted to Mixed-Signal Design (Forum) by Abhishek D on Mon, Feb 10 2014
  • Switched Cap based System Noise Analysis

    Hi, I am very new to noise analysis when it comes to switched capacitor based system. In my system I have a comparator which goes into unity feedback mode with some frequency. I have also a capacitor which either connects from input of comparator and ground or input of comparator and input to be compared...
    Posted to Mixed-Signal Design (Forum) by Abhishek D on Sat, Feb 8 2014
  • ncelab: *F,AMSCBINER: Unexpected error encountered

    Hi, I am trying to run AMS simulation on IC6.1.5 but everytime I try to run the simulation, I get the following error at the elaboration stage: ncelab: *F,AMSCBINER: Unexpected error encountered when processing spice file during elaboration The help (nchelp) on the error says: irun/AMSCBINER = The program...
    Posted to Mixed-Signal Design (Forum) by beevlsi on Tue, Oct 22 2013
  • DAC Panel: Users Describe Mixed-Signal Verification Challenges, Solutions

    Should analog/mixed-signal verification be more like digital verification, with separate verification teams, a methodology like the Universal Verification Methodology (UVM), and metric-driven verification (MDV)? Yes, according to three mixed-signal engineers at a panel discussion at the Cadence EDA360...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Jun 13 2011
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