	Login with a Cadence account.
Not a member yet? Create a permanent login account to make interactions with Cadence more conveniennt. Register \| Membership benefits

Get email delivery of the Cadence blog (individual posts).

Popular Tags

Browse All Tags

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Send yourself a copy

Cadence RSS Feeds

Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.

Contact Us

Cadence Contacts

Global Office Locator
Find Offices worldwide »

Sales Inquiry
Request for Product information »
Cadence Channel Partners »

Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Send Yourself A Copy

mixed signal

Press Release About TSMC Flow, Blog from ARM Validate Cadence’s Mixed-Signal and 20nm Leadership

A press release and a blog post caught my attention this week (October 15, 2012), and they have clearly demonstrated Cadence's leadership in 20nm process nodes and mixed-signal solutions. The press release is titled " TSMC Selects Cadence Virtuoso and Encounter Platforms for its 20nm Design...

Posted to Mixed-Signal Design (Weblog) by Sathish Bala on Fri, Oct 19 2012
Packed House Expected for Cadence Low-Power Technology Summit

It looks like it might be standing room only for latecomers to the Low-Power Technology Summit at Cadence headquarters building 10 auditorium this Thursday (18 October). Registration has been very strong. I'm expecting a great day -- we have a full agenda covering multiple aspects of low-power design...

Posted to Low Power (Weblog) by Pete Hardee on Tue, Oct 16 2012
Webinar: Is SystemVerilog the Future of Mixed-Signal Modeling?

Real number modeling (RNM) provides a fast way to run a chip-level simulation with analog values, but support for it in the current SystemVerilog Language Reference Manual (2009 LRM) is very limited. A recently archived webinar shows how the next SystemVerilog LRM (which may be dated 2012 or 2013) offers...

Posted to Industry Insights (Weblog) by rgoering on Thu, Oct 4 2012
Panel: Mixed-Signal Designers Reveal “Gaps” and Solutions

Are we closing the gaps in mixed-signal design? That question was posed to five panelists, including three Cadence customer representatives, at the Mixed-Signal Technology Summit held at Cadence Sept. 20, 2012. While panelists noted progress in mixed-signal design tools and flows, they pointed to a number...

Posted to Industry Insights (Weblog) by rgoering on Mon, Oct 1 2012
Keynote: From “Tribulations” to Mixed-Signal Success at Texas Instruments

Texas Instruments has experienced many "tribulations" in mixed analog and digital design, according to Chris Collins, a director at Analog Design Services at TI. But significant progress is underway. At a keynote speech at the recent Mixed-Signal Technology Summit held at Cadence Sept. 20,...

Posted to Industry Insights (Weblog) by rgoering on Wed, Sep 26 2012
Digital Logic in Analog Block – How Will You Test It?

Analog IP blocks these days have increasing amounts of digital control logic. With very small amounts of digital logic, it's possible to just draw gates on the schematic and run targeted tests that will hopefully catch any errors. But when you have several thousand digital gates, a new approach is...

Posted to Industry Insights (Weblog) by rgoering on Mon, Sep 10 2012
Mixed-Signal Methodology Guide Authors Speak Out

Cadence recently published the Mixed-Signal Methodology Guide , a first-of-its-kind book that offers a comprehensive review of the design, verification and implementation techniques required for today's complex mixed-signal designs. The book has 11 lead authors, including three from outside Cadence...

Posted to Industry Insights (Weblog) by rgoering on Thu, Sep 6 2012
Learn From Expert Designers at Mixed-Signal Technology Summit

If you're involved in any phase of mixed-signal design and verification -- or someday might be -- you'll find a lot of valuable, practical information at the Cadence Mixed-Signal Technology Summit Sept. 20, 2012 in San Jose, California. In addition to Cadence R&D experts, you'll hear...

Posted to Industry Insights (Weblog) by rgoering on Thu, Aug 30 2012
Designer View – Using Metric-Driven Verification for Mixed-Signal IP

Can digital verification techniques such as verification planning, coverage metrics, and assertion checking be applied to the analog/mixed-signal world? Yes, according to Pierluigi Daglio, analog verification engineer at STMicroelectronics. In a recorded presentation at the Cadence web site, he shows...

Posted to Industry Insights (Weblog) by rgoering on Wed, Aug 29 2012
Mixed Signal Design IP Embraces Metric-Driven Verification Using RNM

Even though it's been over 2 months since this year's Design Automation Conference in San Francisco, I am still surprised by the response that metric-driven, mixed-signal verification gets from our design community. Cadence had quite a few customer presentations at the EDA360 Theater at DAC this...

Posted to Mixed-Signal Design (Weblog) by Sathish Bala on Mon, Aug 27 2012

Page 3 of 11 (109 items) < Previous 1 2 3 4 5 Next > ... Last »

Popular Tags

Email

Share

Subscribe

Contact Us

mixed signal

Press Release About TSMC Flow, Blog from ARM Validate Cadence’s Mixed-Signal and 20nm Leadership

Packed House Expected for Cadence Low-Power Technology Summit

Webinar: Is SystemVerilog the Future of Mixed-Signal Modeling?

Panel: Mixed-Signal Designers Reveal “Gaps” and Solutions

Keynote: From “Tribulations” to Mixed-Signal Success at Texas Instruments

Digital Logic in Analog Block – How Will You Test It?

Mixed-Signal Methodology Guide Authors Speak Out

Learn From Expert Designers at Mixed-Signal Technology Summit

Designer View – Using Metric-Driven Verification for Mixed-Signal IP

Mixed Signal Design IP Embraces Metric-Driven Verification Using RNM