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mixed signal,EE Times

  • Low-Power Design? Brian Bailey Gets It

    Hats off to Brian Bailey! If you haven't been following his EDA Designline Power Series on eetimes.com you have been missing out. Throughout April, he's been running a pretty comprehensive series of editorials, opinion pieces and contributed articles on the subject of low power design. As he...
    Posted to Low Power (Weblog) by Pete Hardee on Wed, May 2 2012
  • Panelists Discuss Solutions to SoC IP Integration Challenges

    Semiconductor intellectual property (IP) reuse makes system-on-chip (SoC) design possible, but complex SoCs pose some really tough IP integration challenges. Panelists at the May 12 EE Times System on Chip "Virtual Event" answered five questions posed by moderator Mike Demler, technical editor...
    Posted to Industry Insights (Weblog) by rgoering on Sun, May 15 2011
  • Panelists: How to Manage Power for Mixed-Signal and RF

    Nearly all of the discussion about low-power design has been on the digital side - but many of the problems are in the analog/mixed-signal and RF domains. I was thus pleased to see that the EE Times Advances in Power Management on-line conference Sept. 16 had a panel on this topic, with speakers from...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Sep 20 2010
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