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mixed signal design,veriloga

  • Mixed-Signal Simulation Speed Optimization

    After spending some time to setup a mixed-signal simulation, I reached a point where I can no longer increase the simulation speed. The chip core is referencing behavioral VHDL and a majority of the analog modules are represented by Verilog-A code. I am simulating using irun. I was wondering it if would...
    Posted to Custom IC Design (Forum) by TjaartOpperman on Tue, Jul 17 2012
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