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mixed signal design

CADENCE capacitor corners max min typ meaning

Hi all, Please anyone can tell me what is the meaning of max, min, and typ for capacitors corners. I understand that the parameters ss or ff corresponds to the mobility ( slow slow, fast fast) of the electrons in MOS devices. But i don´t understand what are the changes in the model of the capacitors...

Posted to Mixed-Signal Design (Forum) by Ricardo Alves on Mon, Jun 17 2013
Virtuoso Verilog Environment for NC-Verilog integration

Hi all, Through Virtuoso Verilog Environment for NC-Verilog Integration ，I initialize a analog design ,then setup netlist explicitly option to ture. I hope to generate that the netlister used the pin name method as following . The result is out of my expectation. some part of netlist remain the pin order...

Posted to Mixed-Signal Design (Forum) by Provence on Wed, Jun 5 2013
How often does AMS flush outputs by default during a simulation?

Iam running a long transient simulation using AMS designer. I would like to flush the simulation results periodically in order to view results as the simulation progresses. Do we have flushpoints and flushtime(s) options available in AMS just as we have in spectre? Please suggest me.I am using INCSIV...

Posted to Mixed-Signal Design (Forum) by royK on Wed, May 22 2013
Mixed Signal Technology Summit Proceedings Now Available

In September 2012, Cadence held its second Mixed-Signal Summit in San Jose, California. 150 users attended the Summit. The full day program was packed by user presentations. Strong participation and attendance was yet another confirmation of increased design activities in the mixed-signal area. Attendees...

Posted to Mixed-Signal Design (Weblog) by nizic on Thu, Dec 13 2012
Mixed-Signal Technology Summit in Japan Provides Technology Updates

Japan’s semiconductor industry is undergoing a significant change in recent years. We are seeing a shrinking business in SoC development while design and semiconductor companies are trying to focus more on higher profitable and differentiable products like microcontrollers and power management...

Posted to Mixed-Signal Design (Weblog) by QiWang on Thu, Nov 29 2012
Recent Events Show That Customer Interest in Mixed-Signal Remains High

The well attended Mixed-Signal Technology Summit last month really demonstrated the tremendous interest our customers have in learning new methodologies and techniques for mixed-signal designs. I would like to share some interesting data points based on a survey from the attendees of the event. Among...

Posted to Mixed-Signal Design (Weblog) by QiWang on Tue, Oct 30 2012
Mixed-Signal Simulation Speed Optimization

After spending some time to setup a mixed-signal simulation, I reached a point where I can no longer increase the simulation speed. The chip core is referencing behavioral VHDL and a majority of the analog modules are represented by Verilog-A code. I am simulating using irun. I was wondering it if would...

Posted to Custom IC Design (Forum) by TjaartOpperman on Tue, Jul 17 2012
Mixed-Signal Gets Clear Message in China

While most of my colleagues in the US were taking a nice break during the July 4 th week, a small group of people including me was on the road for a mixed-signal Tech-on-Tour in China. There was some debate internally on whether designers in China would be interested in such a topic. What we had experienced...

Posted to Mixed-Signal Design (Weblog) by QiWang on Tue, Jul 10 2012
What’s Hot for Mixed-Signal At DAC?

Analog/mixed-signal design is a hot topic at the Design Automation Conference! At DAC 2012 at San Francisco's Moscone Center next week (June 4-7), you can keep up with the latest developments in mixed-signal design methodology, including design, implementation and verification. You will find it is...

Posted to Mixed-Signal Design (Weblog) by QiWang on Thu, May 31 2012
Cadence To Release the Industry's First Mixed-Signal Methodology Book

The new era of “Internet Everywhere” creates a whole new spectrum of applications, ranging from health care, automotive, to entertainment and cloud computing, which demand more and more mixed-signal and low power designs. In fact, mixed-signal applications have become one of the fastest growing...

Posted to Mixed-Signal Design (Weblog) by QiWang on Sat, May 26 2012

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mixed signal design

CADENCE capacitor corners max min typ meaning

Virtuoso Verilog Environment for NC-Verilog integration

How often does AMS flush outputs by default during a simulation?

Mixed Signal Technology Summit Proceedings Now Available

Mixed-Signal Technology Summit in Japan Provides Technology Updates

Recent Events Show That Customer Interest in Mixed-Signal Remains High

Mixed-Signal Simulation Speed Optimization

Mixed-Signal Gets Clear Message in China

What’s Hot for Mixed-Signal At DAC?

Cadence To Release the Industry's First Mixed-Signal Methodology Book