Home > Community > Tags > mixed signal design
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

mixed signal design

  • Magnetic Tunneling Junction (MTJ)- HSpice file simulation in ADE -Cadecne Virtuoso

    Hi, I am working on modeling of STT-MTJ using Cadecne Virtuoso. I am trying to simulate model ' MTJT.inc ' ( Ref : - Jon Harm, Farbod Ebrahimi- Univertsity of Minnesota ) using Cadence Virtuoso Spectre. I have following doubt :- MTJ as a device, how do I instantiate a this H-spice sub-circuit...
    Posted to Custom IC Design (Forum) by AkashUB on Sat, Sep 13 2014
  • bus value export to table

    I am working on an ADC. I would like to be able to export the value of the output bus to a table. Basically I have an n-bit hexadecimal bus and a trigger signal. I am using Visualization & Analysis XL. I would like to have a table on the screen or a file that reports the value of the bus on the falling...
    Posted to Mixed-Signal Design (Forum) by Bob Mounger on Fri, Aug 22 2014
  • Re: mixed signal simulation

    thanks for your valuable guidance.... sir, in my project i have designed one block in verilog.Now i need to integrate it to the remaining analog blocks. so i generate verilog netlist of the corresponding digital block. But after integrating it with analog block i need to check functional and transistor...
    Posted to Mixed-Signal Design (Forum) by KUMARJAYA on Thu, Jul 17 2014
  • mixed signal simulation

    is it possible to simulate verilog netlist in cadence virtuoso?how to bind the standard netlist cell to the corresponding code?
    Posted to Mixed-Signal Design (Forum) by KUMARJAYA on Wed, Jul 9 2014
  • Mathematical explanation for resistor mismatch parameters

    Can someone please provide the formulas for the mismatch parameters (used in DCMATCH analysis): mrl mrlp mrw mrwp mrlw1 mrlw1p mrlw2 mrlw2p. I could not find the corresponding equations in the Spectre manuals. Thanks!
    Posted to Custom IC Design (Forum) by cadwiz on Tue, Jun 10 2014
  • Vhdl-ams beginner

    Hi, I'm really new in vhdl-ams, I write my firsts codes in this langage and I have some issues to understand some basics of this extension. My tutor want me to describe an analogic comparator and test it with a ramp waveform. A schema of this circuit is in attachment. I don't know how to connect...
    Posted to Mixed-Signal Design (Forum) by sebgimi on Tue, Feb 11 2014
  • Re: Switched Cap based System Noise Analysis

    Hi Andrew, Previously I gave some incorrect information. My flow is like that 1) Comparator sampling bandgap charge @ 400 Khz 2) Comparator sampling input charge @ 400 Khz but after 1. ( Phase lag ) 2) Caps are connecting disconnecting @ 2 Mhz Best Regards Abhishek
    Posted to Mixed-Signal Design (Forum) by Abhishek D on Mon, Feb 10 2014
  • Re: Switched Cap based System Noise Analysis

    Hi Andrew, Following are the details- 1) Comparator goes to unity feedback and then openloop - 222.22k 2) There are some caps and they either get connected b/w input of comparator and Supply or Input of comparator and ground- 2MHz 3) There is one switched cap BGREF. When comparator goes in unity feedback...
    Posted to Mixed-Signal Design (Forum) by Abhishek D on Mon, Feb 10 2014
  • Re: Switched Cap based System Noise Analysis

    Hi Andrew, Thank you for being always first to answer. I referred your attachment before putting my query. But this says, it takes only one clock. In my system multiple switchings are happening and that too at different rates. Pardon my ignorance if I am not able to understand the material you attached...
    Posted to Mixed-Signal Design (Forum) by Abhishek D on Mon, Feb 10 2014
  • Switched Cap based System Noise Analysis

    Hi, I am very new to noise analysis when it comes to switched capacitor based system. In my system I have a comparator which goes into unity feedback mode with some frequency. I have also a capacitor which either connects from input of comparator and ground or input of comparator and input to be compared...
    Posted to Mixed-Signal Design (Forum) by Abhishek D on Sat, Feb 8 2014
Page 1 of 4 (36 items) 1 2 3 4 Next >