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mixed signal design

  • OSCILLATOR DESIGN

    I am new to AMS language and design and I am trying to model an oscillator with the following features : a. The oscillator operates at a default freq of say 32Khz, with tuning applicability from 20Khz to 50Khz. b. The oscillator operates in two power domains, one of 3.3v and other of 1.2v. c. When the...
    Posted to Mixed-Signal Design (Forum) by Sayantan55 on Sun, Sep 15 2013
  • can we attach technology file to verilog-AMS design

    Hai all I am new to cadence and verilog-AMS i am trying to design ADC circuit completely in verilog-AMS description. i have a doubt that whether we can attach technology file(65nm or 180nm) to this design codes and get the power consumption of the circuit .if any one says yes we can then tell me how...
    Posted to Mixed-Signal Design (Forum) by sunilreddy on Fri, Aug 16 2013
  • Re: about 64 - 32 bit binaries (ultrasim64)

    Dear Andrew, Thanks for your quick reply. Indeed I cannot run Ultrasim in 64bit mode. Below is the message I get: Connecting to License Server ... Done. Error found by UltraSim. ERROR (USIM-12701): The UltraSim-Verimix (mixed mode) simulator option is not compatible with 64-bit platforms. The UltraSim...
    Posted to Mixed-Signal Design (Forum) by Thodoros on Fri, Jul 5 2013
  • about 64 - 32 bit binaries (ultrasim64)

    Hello, At the tool path "..../MMSIM101/tools/ultrasim/bin" I see the link to executable ultrasim64. However I have to exclude ultrasim from the 64bit tools in order to run (my machine is i5 and tools run on centOS). Is there a way to use 64bit binaries for ultrasim ? Another question: I use...
    Posted to Mixed-Signal Design (Forum) by Thodoros on Wed, Jul 3 2013
  • Designing Digital FIR Filter using Cadence Tools

    Hello everyone, I am required to design FIR filter using Cadence tools for one of the projects that I am currently doing. I would like to mention that I am very new to this and have never done filter designing in cadence. Even have very minimal experience in Filter design in MATLAB. Thats why I am not...
    Posted to Mixed-Signal Design (Forum) by indra0804 on Wed, Jul 3 2013
  • CADENCE capacitor corners max min typ meaning

    Hi all, Please anyone can tell me what is the meaning of max, min, and typ for capacitors corners. I understand that the parameters ss or ff corresponds to the mobility ( slow slow, fast fast) of the electrons in MOS devices. But i don´t understand what are the changes in the model of the capacitors...
    Posted to Mixed-Signal Design (Forum) by Ricardo Alves on Mon, Jun 17 2013
  • Virtuoso Verilog Environment for NC-Verilog integration

    Hi all, Through Virtuoso Verilog Environment for NC-Verilog Integration ,I initialize a analog design ,then setup netlist explicitly option to ture. I hope to generate that the netlister used the pin name method as following . The result is out of my expectation. some part of netlist remain the pin order...
    Posted to Mixed-Signal Design (Forum) by Provence on Wed, Jun 5 2013
  • How often does AMS flush outputs by default during a simulation?

    Iam running a long transient simulation using AMS designer. I would like to flush the simulation results periodically in order to view results as the simulation progresses. Do we have flushpoints and flushtime(s) options available in AMS just as we have in spectre? Please suggest me.I am using INCSIV...
    Posted to Mixed-Signal Design (Forum) by royK on Wed, May 22 2013
  • Mixed Signal Technology Summit Proceedings Now Available

    In September 2012, Cadence held its second Mixed-Signal Summit in San Jose, California. 150 users attended the Summit. The full day program was packed by user presentations. Strong participation and attendance was yet another confirmation of increased design activities in the mixed-signal area. Attendees...
    Posted to Mixed-Signal Design (Weblog) by nizic on Thu, Dec 13 2012
  • Mixed-Signal Technology Summit in Japan Provides Technology Updates

    Japan’s semiconductor industry is undergoing a significant change in recent years. We are seeing a shrinking business in SoC development while design and semiconductor companies are trying to focus more on higher profitable and differentiable products like microcontrollers and power management...
    Posted to Mixed-Signal Design (Weblog) by QiWang on Thu, Nov 29 2012
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