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DVCon Paper: UVM-MS Brings Metric-Driven Verification to Mixed-Signal SoCs
Nearly all systems-on-chip (SoCs) are mixed-signal, and they must all be verified. While digital verification is heavily automated, analog verification is still a manual process, making mixed-signal verification extremely challenging. Can we bring digital verification technology, such as metric-driven...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Mar 12 2012
What's Good About ADW’s Server Metrics? Check out the 16.5 Release and See!
The Allegro Design Workbench (ADW) 16.5 has the capability of providing usage metrics. By enabling analysis of the software environment, this enhances software serviceability and reduces IT costs. The ADW Server metrics are based on the ADW Server technology and enables metrics data to be collected from...
Posted to
PCB Design
(Weblog)
by
Jerry GenPart
on Tue, Feb 14 2012
Archived Webinar: Which Verification Coverage Metrics to Use When
What metrics matter most at different stages of the verification process? How can metrics be leveraged to reduce the risk of failures in your IC designs? These questions were answered in a recently archived Cadence webinar that offers a comprehensive primer on the use of code coverage, functional coverage...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Nov 14 2011
Free Webinars Explore Advanced Functional Verification Techniques
UVM, assertion-based simulation, metric-driven verification, assertion synthesis, formal scoreboarding -- these are just a few of the advanced techniques that can improve your verification productivity. To help you learn about such techniques, Cadence is offering a series of nine free one-hour webinars...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Aug 15 2011
DVClub: New User Verification Presentations, Upcoming Free Lunches
For some time now, IC verification engineers have been gathering at quarterly meetings in 10 cities around the world for lunch meetings that include networking and presentations. This happens through DVClub, which has new events coming up for August in Austin and Silicon Valley, and has just posted user...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Aug 9 2011
A Modest Proposal: Using Formal to Close Coverage Gaps
In my last blog post , I summarized some of our activities at DVCon and mentioned briefly the "Birds of a Feather" (BoF) panel and discussion on "Strategies in Verification for Random Test Generation: New Techniques and Technologies" held Monday evening. Today I'd like to fill...
Posted to
Functional Verification
(Weblog)
by
tomacadence
on Fri, Mar 11 2011
My Wish List For The New Decade
Okay, it's the holiday season and end of the year, so I'll combine it all and make a wish list for the new year (as it relates to chip design). Heck, it's the end of the decade - so why not make a wish list for the new decade? A decade is a long time in our industry. This year, my 7-year...
Posted to
Logic Design
(Weblog)
by
Jack Erickson
on Tue, Dec 29 2009
It’s All In The Metrics
You could be forgiven for thinking that this was going to be a discussion of the benefits of imperial versus metric units, but its not. The metrics I’m talking about are those business metrics that constrain a design. These business metrics may be anything from cost, to part quality to RoHS compliance...
Posted to
PCB Design
(Weblog)
by
MattB
on Wed, Mar 18 2009
Design Metrics - ARM is Onto Something
We here at the Logic Design blog seem fascinated with improving design metrics . Why is that? Perhaps we've seen too many designs go through "long loop" iterations later in the cycle because improper metrics were used to determine the design's "goodness" early in the cycle...
Posted to
Logic Design
(Weblog)
by
Jack Erickson
on Mon, Feb 23 2009
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