Log In
|
Register
|
Resource Library
|
Worldwide
Asia-Pacific
|
China
|
EMEA
|
India
|
Israel
|
Japan
|
Korea
|
Taiwan
|
Global Office Locator
Solutions
Products
Services
Support & Training
Alliances
Community
About Cadence
Solutions:
Design IP
Mixed-Signal
Low-Power
Advanced Node
Enterprise Verification
Hosted Design
System Development Suite
Solutions Home
Products for:
System Design and Verification
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Manufacturability Signoff
More Products
OrCAD Products
Design IP
Verification IP
IP Catalog
Products A-Z
Products Home
Capabilities and Practices
Methodology Services
Design Services
DFM Services
Educational Services
Programs
SOI Design Hub
Services Home
Support
Support Offerings
Support Process
Cadence Online Support
Software Downloads
Computing Platform Support
University Software Program
Training
Training Options
Training Course Catalogs
Support & Training Home
Programs and Initiatives
System Realization Alliance
Foundry Program
IP Alliances
ChipEstimate.com - Chip Planning Portal
Connections Program
Verification Alliance Program
Channel Partner (VARs) Program
Power Forward Initiative
Standards and Languages
PCB Service Bureaus
Industry Memberships
Alliances Home
Communities
Industry Insights Blog
Low Power Blog
Mixed-Signal Design Blog
System Design and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Quicklinks
All Blogs
All Forums
Community Search
CDN
Live!
User Conferences
Community Home
EDA Vision
Visit the EDA360 microsite
News and Events:
Newsroom
Events and Webinars
Resources:
Customer Success
Newsletters
Publications
Multimedia Center
Logos
Company Info:
Investor Relations
Executive Team
Careers
Contact Us
About Cadence Home
Home
>
Community
>
Tags
> metric-driven verification
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.
Register
|
Membership benefits
Get email delivery of the Cadence blog (individual posts).
Industry Insights
Low Power
Mixed-Signal Design
System Design
and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Manufacturability Signoff
All Blog Categories
Popular Tags
Allegro
ARM
Custom IC Design
DAC
Digital Implementation
e
EDA360
encounter
ESL
Functional Verification
Incisive
industry insights
Logic Design
Low power
OVM
PCB
PCB design
Specman
System Design and Verification
SystemC
SystemVerilog
TLM
UVM
verification
Virtuoso
Browse All Tags
Share
Email
Social Web
*
Required Fields
Recipients email
*
(separate multiple addresses with commas)
Your name
*
Your email
*
Message
*
Send yourself a copy
Subscribe
RSS
Cadence RSS Feeds
Cadence Press Releases
System Design and Verification Blog
Functional Verification Blog
Digital Implementation Blog
Custom IC Design Blog
RF Design Blog
PCB Design Blog
IC Packaging and SiP Design Blog
Manufacturability Signoff Blog
All Blogs
System Design and Verification Forum
Functional Verification Forum
Digital Implementation Forum
Custom IC Design Forum
Custom IC SKILL Forum
Logic Design Forum
RF Design Forum
PCB Design Forum
PCB SKILL Forum
IC Packaging and SiP Design Forum
Manufacturability Signoff Forum
Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.
Contact Us
Cadence Contacts
Community Relations
Customer Support
Employment
Investor Relations
Media Relations
Training
Global Office Locator
Find Offices worldwide
»
Sales Inquiry
Request for Product information
»
Cadence Channel Partners
»
Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234
*
Required Fields
First Name
*
Last Name
*
Email
*
Company / Institution
*
Comments:
*
Send Yourself A Copy
metric-driven verification
ABV
ABVIP
Acceleration
Accellera
AMS
Analog
analog assertions
analog verification
analog/mixed-signal
ASIC
assertion synthesis
assertion-based verification
assertions
C++
Cadence
Calypto
case splitting
case-splitting
CDNLive
CDNLive!ive!
CDV
Chris Komar
code coverage
coverage
coverage data
coverage driven verification (CDV)
coverage metrics
coverage-driven verification
C-to-Silcon
C-to-Silicon Compiler
DAC
debug
Design Automation Conference
digital
digital verification
Duolos
DVClub
DVCon
DVCon 2012
DVCon paper
EDA360
ESL
formal
Formal Analysis
formal verification
Functional Verification
High-Level Synthesis
IEV
IFV
Incisive
Incisive Enterprise Simulator (IES)
Incisive Enterprise Verifier
Industry Insights
IP modeling
LinkedIn
Low Power
MDV
methodology
metric
metric driven verification (MDV)
metric-driven
metrics
mixed signal
Mixed-Signal
NextOp
OVM
Palladium
Panel
PSL
real number modeling
Silicon Realization
Simulation
SoC
SoC Connectivity
specman
SVA
System Realization
SystemVerilog
Teradyne
testbench
Twitter
UVM
UVM 1.0
UVM-e
UVM-MS
verification
verification closure
verification coverage
Verification IP
Verification IP modeling
verification plan
verification planning
verification strategy
Verilog-AMS
VIP
Virtual Platforms
vPlan
webinar
wreal
Zocalo
Q&A: 7 Years After Verisity – How Specman and e Language Changed IC Verification
Seven years ago this month (April 2005) Cadence acquired Verisity, the pioneering verification company that developed the e language and the Specman environment. The acquisition resulted in a paradigm shift in IC verification, setting the stage for reusable verification methodologies, constrained-random...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Apr 24 2012
DVCon Paper: UVM-MS Brings Metric-Driven Verification to Mixed-Signal SoCs
Nearly all systems-on-chip (SoCs) are mixed-signal, and they must all be verified. While digital verification is heavily automated, analog verification is still a manual process, making mixed-signal verification extremely challenging. Can we bring digital verification technology, such as metric-driven...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Mar 12 2012
Digital and Analog Verification – Round Peg in a Square Hole?
Recently I wrote about a panel discussion that looked at ways of bridging the gap between analog and digital design. This blog post resulted in a lengthy discussion in a LinkedIn group that brought up the topic of verification. One commentator noted that analog and digital designers have very different...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Feb 9 2012
Webinar Report: New Methodology Revs Up Code Coverage Analysis
Most IC verification teams use code coverage as signoff criteria, but they often have limited information about unreachable code. A new "case-splitting" methodology, described in a recently archived webinar, shows how a technique based on formal analysis provides new insight into coverage holes...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Feb 6 2012
Archived Webinar: Which Verification Coverage Metrics to Use When
What metrics matter most at different stages of the verification process? How can metrics be leveraged to reduce the risk of failures in your IC designs? These questions were answered in a recently archived Cadence webinar that offers a comprehensive primer on the use of code coverage, functional coverage...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Nov 14 2011
Report: Formal Analysis Papers at CDNLive India 2011
On October 19, 2011 in Bangalore, India more than 800 engineers across all domains came together for CDNLive India 2011. Among the attendees were over 300 design and verification professionals who focused on the functional and system verification tracks. In this post I'll pull together some highlights...
Posted to
Functional Verification
(Weblog)
by
TeamVerify
on Wed, Oct 26 2011
Webinar: Bringing Digital Verification Methodologies to Mixed-Signal SoCs
It's fairly straightforward (albeit slow) to verify an analog IP block using a Spice simulator. But when that block goes into a mixed-signal system-on-chip (SoC), and the time comes for chip-level verification, a different approach is needed. A recently archived Cadence webinar shows how advanced...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Sep 28 2011
Free Webinars Explore Advanced Functional Verification Techniques
UVM, assertion-based simulation, metric-driven verification, assertion synthesis, formal scoreboarding -- these are just a few of the advanced techniques that can improve your verification productivity. To help you learn about such techniques, Cadence is offering a series of nine free one-hour webinars...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Aug 15 2011
DVClub: New User Verification Presentations, Upcoming Free Lunches
For some time now, IC verification engineers have been gathering at quarterly meetings in 10 cities around the world for lunch meetings that include networking and presentations. This happens through DVClub, which has new events coming up for August in Austin and Silicon Valley, and has just posted user...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Aug 9 2011
Hot Topic: Should Separate Teams Handle Analog Verification?
Dedicated verification teams are well established in the digital world, but not in analog/mixed-signal design. Has the time come for separate analog verification teams? I've been following an ongoing debate on this topic in a couple of LinkedIn groups, a debate that followed my recent blog posting...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Jul 21 2011
Page 1 of 4 (32 items) 1
2
3
4
Next >