Home > Community > Tags > metric driven verification/FPGA
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

metric driven verification,FPGA

  • Designer View: Why We Used Specman for FPGA Verification

    Advanced functional verification techniques like constrained-random test generation are well established for ASICs, but not so much for FPGAs. At a recorded Cadence Theater presentation at the 2013 Design Automation Conference, Torsten KÓ§nig, lead verification architect at Siemens Healthcare, showed...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Sep 16 2013
  • Place and route on SOC encounter

    Hello, I am a newbie at place and route operation. Can anyone please tell me how do you make sure that all the blockes i your design are arranged in a certain way while doing place and route . I mean I have like around 300 odd blockes to be eranged and I want them to be ordered row wise and column wise...
    Posted to Digital Implementation (Forum) by amythpai on Sun, Mar 17 2013
Page 1 of 1 (2 items)