Home > Community > Tags > methodology/e
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

methodology,e

  • DVCon 2013: Functional Verification Is EDA’s “Killer App”

    With another year of record attendance, DVCon has again proven that a functional verification-focused mix of trade show and technical conference is what customers need to get their jobs done. Here are some of the some of the highlights I took away from this informative event: DVCon 2013 was a one stop...
    Posted to Functional Verification (Weblog) by jvh3 on Sun, Mar 10 2013
  • DVCon 2013 for the Specmaniac

    At the upcoming DVCon (in San Jose, CA February 25-28) , Cadence will cover all aspects of our verification technologies and methodologies (full list of Cadence-sponsored events is here ). Of course, Team Specman cannot resist drawing your attention to the many activities that will feature Specman and...
    Posted to Functional Verification (Weblog) by teamspecman on Thu, Feb 7 2013
  • Video: Update on AMIQ’s DVT IDE and UVM 1.0 at DVCon 2011

    The UVM 1.0 release was the big story of DVCon 2011, as it's the first verification methodology officially supported by all three of the "Big 3" simulation vendors. However, the very nature of the standard -- an open source library governed by a community similar in character to Linux itself...
    Posted to Functional Verification (Weblog) by jvh3 on Wed, Apr 6 2011
  • e Verification Job Postings We’ve Seen

    Specmaniacs between jobs: over the last few weeks we’ve seen job postings for verification engineering in general, and e/Specman expertise in specific, in the LinkedIn groups: “Experts in SystemVerilog/Specman/VERA/System C” “Think Verification” “HVL (SystemC/C++/Verilog...
    Posted to Functional Verification (Weblog) by teamspecman on Fri, Aug 6 2010
  • Specman, e, and EDA360

    The EDA industry is all abuzz over the new vision paper "EDA360 - The Way Forward for Electronic Design" ; and for good reason - in 2010 the electronics world is finally starting to transform in ways that have been long anticipated by Specmaniacs and our "Trailblazer" program partners...
    Posted to Functional Verification (Weblog) by teamspecman on Tue, Jun 8 2010
  • Formalizing Multilanguage Mixology For e Users

    Historically it’s been very common for e users to have to mix other programming languages with their e verification environment. Some examples include adding C or C++ reference models, contributing e Universal Verification Components (UVCs) to non- e testbenches, or even interfacing to Matlab models...
    Posted to Functional Verification (Weblog) by teamspecman on Thu, Dec 24 2009
Page 1 of 1 (6 items)