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ISQED Keynote: 20nm From a Custom/Analog Perspective
Most of the discussions about the upcoming 20nm process node have focused on digital design. Not so at the International Symposium on Quality of Electronic Design ( ISQED 2012 ) March 20, where Tom Beckley, senior vice president of R&D for Custom IC and Signoff in the Silicon Realization group at...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Mar 21 2012
Shameless Promotion: Free Club Formal San Jose, Formal Scoreboard Webinar
Please join Team Verify and other D&V engineers for one or both of the following free events over the next 2 weeks: * This coming Tuesday November 8 starting at 11:30am on our San Jose campus, we are holding the next installment of "Club Formal." The main topics for this event will be abstraction...
Posted to
Functional Verification
(Weblog)
by
TeamVerify
on Fri, Nov 4 2011
Free Webinar Thursday 10/13 -- Automating Assertion Generation for Simulation, Formal and Emulation
Everyone can agree that Assertion-Based Verification (ABV) is a powerful methodology for uncovering corner-case bugs, exposing functional coverage holes, and increasing verification observability. HOWEVER, there is often one teeny-tiny issue that inhibits its wider adoption: hand-writing assertions can...
Posted to
Functional Verification
(Weblog)
by
TeamVerify
on Wed, Oct 5 2011
8 Users Compare RTL Compiler (RC) vs. Design Compiler (DC) on DeepChip.com
It was refreshing to see what happened when John Cooley made his latest request for reader feedback on his popular DeepChip website catering to the semiconductor design community. A request had come in from a previous DeepChip post prior to the Design Automation Conference (DAC) as follows: Are there...
Posted to
Logic Design
(Weblog)
by
David Stratman
on Mon, Jun 20 2011
Guest Blog: What UVM Needs to Succeed
The Universal Verification Methodology (UVM) is a big step forward for verification IP interoperability, but it needs to be embraced as part of a bigger, broader, people-centric definition of methodology, according to Neil Johnson, principal consultant at Cadence partner and design services provider...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Apr 21 2011
1st Anniversary of the Team Verify Blog!
Verifiers rejoice: today is the 1st anniversary of the launch of this blog!!! To commemorate the occasion, allow us to highlight the top 5 posts (out of 25 total!) from the past year. Without further adieu, in ascending order of web hits and comments received ... #5 - "Everything Assertion Based"...
Posted to
Functional Verification
(Weblog)
by
TeamVerify
on Mon, Apr 11 2011
Video: Update on AMIQ’s DVT IDE and UVM 1.0 at DVCon 2011
The UVM 1.0 release was the big story of DVCon 2011, as it's the first verification methodology officially supported by all three of the "Big 3" simulation vendors. However, the very nature of the standard -- an open source library governed by a community similar in character to Linux itself...
Posted to
Functional Verification
(Weblog)
by
jvh3
on Wed, Apr 6 2011
Save The Date: Free Webinar on Automated SoC Connectivity Verification This Thursday March 24
We interrupt our technically oriented blogging to shamelessly promote a free webinar we are giving on SoC Connectivity checking this Thursday March 24 at 10am-11am Pacific time. At first glance, this topic doesn't seem like such a big deal - after all, checking IP-to-IP and point-to-multi-point connections...
Posted to
Functional Verification
(Weblog)
by
TeamVerify
on Fri, Mar 18 2011
Video: Optimizing Area and Power Using Formal Methods
At DVCon 2011, a paper presented by Freescale and Cadence described a truly novel application of formal technology for something completely different than assertion-based verification (ABV). Specifically, the authors used formal engines to optimize the selection of complex (read, "higher in area...
Posted to
Functional Verification
(Weblog)
by
TeamVerify
on Tue, Mar 8 2011
Celebrating the UVM 1.0 Release, or the Gadfly Eats a Little Crow
As I hope you have all seen by now, Accellera has announced the official production release of the Universal Verification Methodology (UVM) 1.0 standard. My colleagues Richard Goering , Stan Krolikoski and Adam Sherer have already blogged about the release and its contents so I'll refer you to their...
Posted to
Functional Verification
(Weblog)
by
tomacadence
on Tue, Feb 22 2011
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