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memory

How IP Subsystem Will Speed NVM Express (NVMe) Adoption

Non-Volatile Memory Express (NVM Express or NVMe) is an emerging protocol standard for accessing solid state drives (SSDs) over PCI Express (PCIe) links. It would thus make sense, if you're designing an SoC that has an SSD interface, to cobble together a subsystem that includes an NVMe controller...

Posted to Industry Insights (Weblog) by rgoering on Tue, May 15 2012
Specman’s Memory Management Orientation Guide (or “Honey – Please Take out the Garbage”)

Memory management is not something the Specman user is supposed to worry about. Nobody likes to make notes about allocations and freeing up memory segments when he's programming, and Specman supplies a mechanism that allows the programmer to have some extra time for a cup of coffee. Unfortunately...

Posted to Functional Verification (Weblog) by teamspecman on Fri, May 11 2012
Modeling Large Memories in SystemC

Sometimes Virtual Platforms model systems with large amounts of memory. Many embedded systems have a gigabyte or more of SDRAM. For example, one of the Xilinx Zynq boards, known as ZC702, has a Linux Device Tree source file defining the memory size as 0x40000000, or 1 Gb. Thinking about a SystemC model...

Posted to System Design and Verification (Weblog) by jasona on Fri, Apr 13 2012
EDA Symposium: How Wide I/O is Driving 3D-ICs with TSVs

Any new technology needs a driving force or "killer app," and 3D-ICs with through-silicon vias (TSVs) are no exception. By allowing a high-bandwidth, low-power connection between CPU and DRAM, the new JEDEC wide I/O mobile DRAM standard will be that driving force, according to Marc Greenberg...

Posted to Industry Insights (Weblog) by rgoering on Tue, Apr 10 2012
Open NAND Flash Interface (ONFi 3.0) – Faster Throughput for SoC Designs

Memory is an important part of virtually every electronic system, yet it's increasingly becoming a performance bottleneck. The latest ONFi 3.0 (Open NAND Flash Interface) specification promises to ease this bottleneck for nonvolatile memory. But silicon IP support is needed to facilitate adoption...

Posted to Industry Insights (Weblog) by rgoering on Mon, Jan 9 2012
The Denali Memory Report has Returned!

For more than a decade, the Denali Memory Report has been an authoritative source of information about business and technology trends in semiconductor memory and storage. The report was published by Denali Software, which was acquired by Cadence in 2010. Now the report has returned as the Denali Memory...

Posted to Industry Insights (Weblog) by rgoering on Thu, Jan 5 2012
An Update on the JEDEC Wide I/O Standard for 3D-ICs

One of the big advantages of 3D-ICs with through-silicon vias (TSVs) is the potential for much faster memory bandwidth compared to conventional 2D ICs. That's why the emerging JEDEC wide I/O mobile DRAM memory standard, which takes full advantage of 3D die stacking to provide significant power and...

Posted to Industry Insights (Weblog) by rgoering on Thu, Dec 15 2011
Three Die Stack -- A Big Step “Up” for 3D-ICs with TSVs

A major advancement in 3D-IC through-silicon via (TSV) design will be unveiled Tuesday (Dec. 13) as representatives of CEA-LETI and ST-Ericsson describe the development of a three-die stack with wide I/O memory and logic. This tapeout is the result of a collaboration between these two organizations and...

Posted to Industry Insights (Weblog) by rgoering on Tue, Dec 13 2011
ARM TechCon Paper: Why DRAM Latency is Getting Worse

There's a general view that everything gets faster and better as technology advances, but when it comes to external memory latency, that's not the case. In a recent ARM TechCon paper Marc Greenberg, director of product marketing at Cadence, showed why DRAM latency is increasing and discussed...

Posted to Industry Insights (Weblog) by rgoering on Thu, Nov 17 2011
Seven Emerging Mobile Device Standards – and How to Verify Them

Seven emerging protocol and memory interface standards are promising to bring new capabilities to smartphones, tablets, and a myriad of other "smart" mobile devices. These new standards will offer unprecedented speed, low latency, low power, and high capacity, dramatically improving the user...

Posted to Industry Insights (Weblog) by rgoering on Mon, Sep 26 2011

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memory

How IP Subsystem Will Speed NVM Express (NVMe) Adoption

Specman’s Memory Management Orientation Guide (or “Honey – Please Take out the Garbage”)

Modeling Large Memories in SystemC

EDA Symposium: How Wide I/O is Driving 3D-ICs with TSVs

Open NAND Flash Interface (ONFi 3.0) – Faster Throughput for SoC Designs

The Denali Memory Report has Returned!

An Update on the JEDEC Wide I/O Standard for 3D-ICs

Three Die Stack -- A Big Step “Up” for 3D-ICs with TSVs

ARM TechCon Paper: Why DRAM Latency is Getting Worse

Seven Emerging Mobile Device Standards – and How to Verify Them