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memory characterization

  • Library "Safe Margins" -- Are They Really Saving Your Design?
    Designers need to radically re-think their strategies for timing closure to get the most out of process technologies that are becoming readily available. The additional burdens of creating electrical cell views for timing, power and signal integrity, accounting for process variability, managing leakage...
    Posted to Custom IC Design (Weblog) by AElzeftawi on Thu, Jan 10 2013

  • Is Fast SPICE Simulation Hitting a Wall?
    The transistor-level SPICE simulator has been the gold standard for custom/analog verification for decades. But SPICE is too slow for many applications in which transistor-level accuracy is needed. So-called "Fast SPICE" simulators can provide considerable speedups -- but current Fast SPICE...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Nov 19 2012
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