Home > Community > Tags > low-power/verification
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

low-power,verification

  • New Incisive Low-Power Verification for CPF and IEEE 1801 / UPF

    On May 7, 2013 Cadence announced a 30% productivity gain in the June 2013 Incisive Enterprise Simulator 13.1 release . Advanced debug visualization, faster turn-around time, and the extension of eight years of low-power verification innovation to IEEE 1801/UPF are the key capabilities in the release...
    Posted to Low Power (Weblog) by Adam Sherilog on Tue, May 7 2013
  • Assertions Help Avoid Chip Melt

    When asked why the use of assertions for low power is rising, I say “at 40nm and below, the chips are just going to melt.” Ann Steffora Mutschler, you quoted me perfectly in your “ Avoiding Chip Melt ” article! Assertions are just the tip of the low-power verification iceberg...
    Posted to Low Power (Weblog) by Adam Sherilog on Thu, Mar 22 2012
  • Free “Power” Lunch at DVCon Exposes Verification Challenges

    A free lunch, a 50% off deal on a new verification book, and a chance to hear about real-world experiences in low-power verification -- it's all happening Tuesday Feb. 28 at the DVCon 2012 conference in San Jose, California. The Cadence-sponsored lunch, which runs from 12:30 pm to 2:00 pm, is titled...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Feb 22 2012
  • Cadence Low-power Verification: Tear Down These Walls

    You've been building chips for years and the growing complexity means you just can't tolerate simple tool-to-tool flows and group-to-group barriers any more. SystemC and RTL in the same low-power simulation? Got it. Mixed-signal? Yep. Every team with fingers in the power intent? For sure. Siicon...
    Posted to Low Power (Weblog) by Adam Sherilog on Tue, Nov 2 2010
  • Talk "Low Power" With The Experts

    I am very excited about an event that Cadence low-power R&D and technical experts are hosting in Europe and eventually in other regions. The nice part about this is that it allows for informal discussions between engineers. I recently sat down with one of the presenters to find out what these events...
    Posted to Digital Implementation (Weblog) by soheilm1 on Mon, Mar 9 2009
Page 1 of 1 (5 items)