Home > Community > Tags > low-power design
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

low-power design

  • Low-power Keeps Gate-Level Simulation Forever Young

    Ann Mutschler blogged in the Low-Power Engineering Community that gate-level simulation is coming back, driven in part by low-power verification needs. “In a small sense, what’s old is new” may actually be the biggest understatement in her blog. Ann attributes the observation to Cadence’s...
    Posted to Low Power (Weblog) by Adam Sherilog on Thu, Sep 8 2011
  • An Expert’s View on Power Formats and Methodology

    In the last five years since the introduction of power formats, using a side file to describe power intent such as power domains, power modes and associated interface logic has become the mainstream low power design methodology. This marks great progress toward automating complex low power design techniques...
    Posted to Low Power (Weblog) by Pete Hardee on Wed, Aug 24 2011
  • Low Power Design -- Alive and Well at DAC

    Low power design was undoubtedly one of the themes of DAC this year -- especially at the Cadence booth. We drew lively interest on the DAC floor with our low power demo station, which was continuously busy especially on the free Monday. We were showing a new demo explaining how advanced low power techniques...
    Posted to Low Power (Weblog) by Pete Hardee on Tue, Jun 14 2011
  • GUC User Presentation at DAC: How to Do Low Power Design

    Power was clearly a hot topic at the recent Design Automation Conference (DAC). Many companies demonstrated their unique tool capabilities to address power issues at different abstraction levels. However, we saw very few presentations that offered a user perspective on how they do low power designs and...
    Posted to Low Power (Weblog) by QiWang on Mon, Jun 13 2011
  • ARM Keynote: Some Inconvenient Truths About Low-Power Design

    While there have been many advances in low-power IC design, it still involves tough choices and poses difficult questions, according to Rob Aitken, R&D fellow at ARM. Aitken talked about the myths and realities of low-power design in a keynote speech at the recent IEEE Electronic Design Processes...
    Posted to Industry Insights (Weblog) by rgoering on Sun, Apr 17 2011
  • Let’s Bring Analog Into Low-Power Design Discussion

    The discussion about low-power IC design has been focused on digital implementation from RTL on down. We are beginning to move above RTL with tools and methodologies that consider power at a systems level. But what’s not so often discussed is the use of low-power design in mixed digital and analog...
    Posted to Industry Insights (Weblog) by rgoering on Fri, Sep 11 2009
  • Guest Blog: Understand Your Objectives For Low Power Design

    Veteran IC designer Steve Padnos notes that low-power design starts with a clear understanding of objectives – a process that is easy to overlook. He provides suggestions that can help designers meet this challenge. Over the last several years, power has moved from an afterthought to a major concern...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Jun 15 2009
Page 3 of 3 (27 items) < Previous 1 2 3