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New Incisive Low-Power Verification for CPF and IEEE 1801 / UPF
On May 7, 2013 Cadence announced a 30% productivity gain in the June 2013 Incisive Enterprise Simulator 13.1 release . Advanced debug visualization, faster turn-around time, and the extension of eight years of low-power verification innovation to IEEE 1801/UPF are the key capabilities in the release...
Posted to
Low Power
(Weblog)
by
Adam Sherilog
on Tue, May 7 2013
Ultra Low Power Benchmarking: Is Apples-to-Apples Feasible?
I noticed some very interesting news last week, widely reported in the technical press, and you can find the source press release here . In a nutshell, the Embedded Microprocessor Benchmark Consortium (EEMBC) has formed a group to look at benchmarks for ultra low power microcontrollers. Initially chaired...
Posted to
Low Power
(Weblog)
by
Pete Hardee
on Tue, Feb 12 2013
Video, Presentation – Low Power Design with ARM Physical and Processor IP
Most system-on-chip designers have two things in common - use of ARM physical and/or processor IP, and a mandate to reduce power consumption. There's a wealth of information on low-power design with ARM IP in a newly available video, as well as presentation slides, from an hour-long presentation...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Dec 17 2012
Low-Power Technology Summit Proceedings Now Available
On October 18, 2012 Cadence held a Low-Power Technology Summit at our San Jose, California headquarters. Experts from Cadence and other leading companies presented the latest low-power design methodologies. Well, it took us a while but you can now view the material via the Low-Power Technology Summit...
Posted to
Low Power
(Weblog)
by
Pete Hardee
on Wed, Dec 5 2012
Perspective on Power: 2012 Survey Predicts 2013 as the Year of DVFS
The recent Low-Power Technology Summit held at Cadence headquarters in San Jose gave us a great opportunity to take the pulse of low-power design by surveying the attendees. Some of the data we got was expected, but there were a couple of surprises. First, some of the expected stuff. We'd noticed...
Posted to
Low Power
(Weblog)
by
Pete Hardee
on Thu, Nov 29 2012
Jan Rabaey Keynote: For Lower Power, Re-Think Computing
If we want truly energy-efficient servers and mobile devices, existing low-power design techniques are not sufficient, according to Jan Rabaey, professor of electrical engineering and computer science at the University of California at Berkeley. In an animated and provocative keynote speech at the Cadence...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Oct 21 2012
Low-Power Design Case Studies: 15 CDNLive! Papers So Far This Year
CDNLive! is back with a bang in 2012, with very strong support from the Cadence user community worldwide. We're three-quarters the way through the events at the time of writing -- you can see the whole program on www.cadence.com at the CDNLive! 2012 Worldwide page. Proceedings are published so far...
Posted to
Low Power
(Weblog)
by
Pete Hardee
on Mon, Sep 17 2012
Lessons for EDA When Low Power vs. Heat Dissipation Isn’t a Fair Fight: A Case Study With the GoPro Hero2 Camera
Right up there with functional verification, the challenges of low power design and verification present an existential threat to our customers' products, and ultimately their businesses. Clearly both sides of the low power coin -- reducing generated heat and/or increasing efficiency to make the...
Posted to
Functional Verification
(Weblog)
by
jvh3
on Wed, Sep 12 2012
RAK: Conformal Low Power Advanced Features for Power Intent Comparison, Hierarchical Integration and CPF Macro Modeling
Why do you define macro models? Luke Lang , Engineering Director at Cadence, says that "Just because you have a hard macro doesn't mean you need to define a macro model: A single-domain hard macro without any low power component should be black-boxed. A macro model is not necessary." Luke...
Posted to
Low Power
(Weblog)
by
SumeetAggarwal
on Fri, Aug 10 2012
What’s Hot for Mixed-Signal At DAC?
Analog/mixed-signal design is a hot topic at the Design Automation Conference! At DAC 2012 at San Francisco's Moscone Center next week (June 4-7), you can keep up with the latest developments in mixed-signal design methodology, including design, implementation and verification. You will find it is...
Posted to
Mixed-Signal Design
(Weblog)
by
QiWang
on Thu, May 31 2012
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