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Free “Power” Lunch at DVCon Exposes Verification Challenges
A free lunch, a 50% off deal on a new verification book, and a chance to hear about real-world experiences in low-power verification -- it's all happening Tuesday Feb. 28 at the DVCon 2012 conference in San Jose, California. The Cadence-sponsored lunch, which runs from 12:30 pm to 2:00 pm, is titled...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Feb 22 2012
Incisive Performance Scales to Meet Advanced Node SoC Verification Requirements
Its’ all about RTL simulation. I mean gates. I mean turn-around-time. Project-level productivity. Mixed-signal. Low-power. UVM. And. And. And. … And the reality is that advanced node SoCs are so complex that it is truly about all of these. Our new white paper details a systematic approach...
Posted to
Functional Verification
(Weblog)
by
Adam Sherilog
on Mon, Jan 30 2012
Webinar Report: Power-Aware Mixed-Signal Verification
Most of the discussion about low-power design techniques has focused on digital circuits. However, nearly all systems-on-chip (SoCs) are mixed-signal, and the way in which analog and digital circuitry interact has a huge impact on overall power consumption. Thus, low power (or "power aware"...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Jan 25 2012
Low Power Design in 2011 and Predictions for 2012
It's that time of year again - winding down towards the end of the year, taking some time with the family, and looking forward to returning refreshed for a new year. So what was the big news for low power in 2011 and what do we have to look forward to in 2012? It's sometimes humbling to look...
Posted to
Low Power
(Weblog)
by
Pete Hardee
on Thu, Dec 22 2011
Low Power Marketing Hype – And What They Don’t Tell You
Here in the USA, we're just back from the Thanksgiving holiday. This year, I got caught up in "Black Friday," which is the day after Thanksgiving, and one of the biggest shopping days of the year, especially for consumer electronics. I'm afraid to say I was convinced enough by some...
Posted to
Low Power
(Weblog)
by
Pete Hardee
on Wed, Nov 30 2011
Si2 Interoperability Guide V2.0 Available for Download
Recently, the Silicon Integration Initiative (Si2) announced the availability of the Interoperability Guide for Power Format Standards V2.0 . This is an important milestone of power format interoperability between IEEE 1801-2009 and the Common Power Format (CPF). This update was triggered by the Si2's...
Posted to
Low Power
(Weblog)
by
QiWang
on Mon, Oct 31 2011
Si2 Conference: New Directions for Low-Power Standards
The Silicon Integration Initiative (Si2) Conference Oct. 20 provided an ambitious new roadmap for low power standards. Presentations described the current Common Power Format (CPF) 2.0 release, steps towards interoperability with IEEE 1801 (Universal Power Format, UPF), a new approach to power modeling...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Oct 24 2011
Cadence Low Power Guru Wins Si2’s Distinguished Service Award
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Posted to
Low Power
(Weblog)
by
Pete Hardee
on Fri, Oct 21 2011
Another Expert’s View on Power Intent and Hierarchy
Normal 0 false false false EN-US X-NONE X-NONE /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-priority:99; mso-style-qformat:yes; mso-style-parent:""; mso-padding-alt...
Posted to
Low Power
(Weblog)
by
Pete Hardee
on Wed, Sep 21 2011
An Expert’s View on Power Formats and Methodology
In the last five years since the introduction of power formats, using a side file to describe power intent such as power domains, power modes and associated interface logic has become the mainstream low power design methodology. This marks great progress toward automating complex low power design techniques...
Posted to
Low Power
(Weblog)
by
Pete Hardee
on Wed, Aug 24 2011
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