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Electronic System Level (ESL) Design Gets a Pragmatic Look at EDPS Workshop
Presentations at the Electronic Design Process Symposium (EDPS) April 18, 2013 gave a realistic look at the promises and limitations of electronic system level (ESL) design. Speakers noted that ESL tools are used for the lower levels of the software stack, but typically not for applications development...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Apr 21 2013
CDNLive Silicon Valley 2013 Proceedings Available for Download!
CDNLive Silicon Valley, held March 12-13, 2013, featured nearly 100 technical sessions from customers, partners, and Cadence R&D experts. Presentations from most of those sessions are now available on line . Here's your chance to review presentations you heard, catch up on sessions you missed...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Apr 4 2013
Video, Presentation – Low Power Design with ARM Physical and Processor IP
Most system-on-chip designers have two things in common - use of ARM physical and/or processor IP, and a mandate to reduce power consumption. There's a wealth of information on low-power design with ARM IP in a newly available video, as well as presentation slides, from an hour-long presentation...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Dec 17 2012
Q&A: Jiayuan Fang Discusses Sigrity, Cadence Merger, Signal and Power Integrity, and 3D-ICs
In July 2012 Cadence announced its acquisition of Sigrity , a leading provider of signal integrity (SI) and power integrity (PI) analysis tools for chip, package and board. Jiayuan Fang, Sigrity founder and CEO, joined Cadence as vice-president of R&D for high-speed design products in the Silicon...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Dec 12 2012
Panelists: Low Power Design Needs System-Level Boost
When low-power design experts get together, much of the conversation turns to the system level. At least that was the case at the recent Low Power Technology Summit held at Cadence Oct. 18, 2012, where audience members questioned panelists about early power estimation, power modeling, and the role of...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Oct 28 2012
Cadence at ARM TechCon – Verification IP, 14nm FinFET, Low Power, Mixed Signal, and More
With nine technical paper presentations, six sponsored sessions, demos, and exhibits, Cadence will have a strong presence at ARM TechCon in Santa Clara, California Oct. 30-Nov. 1, 2012. Cadence papers and sessions will cover topics including advanced-node digital, mixed-signal, low power, verification...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Oct 23 2012
Jan Rabaey Keynote: For Lower Power, Re-Think Computing
If we want truly energy-efficient servers and mobile devices, existing low-power design techniques are not sufficient, according to Jan Rabaey, professor of electrical engineering and computer science at the University of California at Berkeley. In an animated and provocative keynote speech at the Cadence...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Oct 21 2012
Si2 Talk: Why System-Level Low Power is Challenging
There's a lot of interest in "system level" low power design -- but what does it really mean? "There a lot of confusion," said Pete Hardee, director of solutions marketing at Cadence, in a presentation at the recent Silicon Integration Initiative ( Si2 ) Conference. "What's...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Oct 15 2012
Free Low Power Summit – Dr. Jan Rabaey, ARM, Freescale, and More
If you're involved - or just interested - in any aspect of low-power electronics design, you'll find a lot of good information at a one-day Low-Power Technology Summit at Cadence headquarters in San Jose, California October 18. Highlighting the event is a keynote by Jan Rabaey , professor of...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Sep 24 2012
Designer View – Low-Power IC Design Challenges and Solutions
The IC physical design team at Marvell Technology Group Ltd. has a tough challenge. They're under a lot of pressure to minimize power consumption as much as possible, while getting products out the door quickly. In a recorded presentation at the Cadence web site, Murali Natarajan, senior physical...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Aug 23 2012
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