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low power,IR drop
adaptive
Aitken
Analog
analog IP
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Virtuoso
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Five-Minute Tutorial: Create Encounter Power System (EPS) Power-Grid Views For Standard Cells
In today's tutorial, I'm giving you a sample EPS (Encounter Power System) script that you can use to generate power-grid views for your standard cells. Power-grid views are used during rail analysis, with IR-Drop and EM (electromigration/current density) being the two most popular analysis types...
Posted to
Digital Implementation
(Weblog)
by
Kari
on Fri, Feb 22 2013
Webinar Report: Solving Mixed-Signal Power Grid Challenges
Complex analog/mixed-signal ICs pose many power grid design and analysis challenges. Unanticipated IR drop and electromigration problems are commonplace, and they significantly impact circuit behavior. But as a recently archived webinar shows, there are a number of ways to minimize these problems, even...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Jan 11 2012
ARM Keynote: Some Inconvenient Truths About Low-Power Design
While there have been many advances in low-power IC design, it still involves tough choices and poses difficult questions, according to Rob Aitken, R&D fellow at ARM. Aitken talked about the myths and realities of low-power design in a keynote speech at the recent IEEE Electronic Design Processes...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Apr 17 2011
Digital Centric Mixed-Signal Dynamic Power Verification – Bringing It All Together
This is the final posting in a series of blogs on dynamic power management in digital-centric mixed-signal verification environments. In this post, I will talk about concepts behind digital-centric mixed-signal verification (DMSV). My previous blogs covered some of the following topics: 1. Basics of...
Posted to
Low Power
(Weblog)
by
Neyaz
on Tue, Oct 19 2010
Analog Coverage Metrics in Mixed-Signal Simulations
This posting is part of a series of blogs on dynamic power management in digital-centric mixed-signal verification environments. In this post, I will cover metrics collection from analog circuits during mixed-signal simulation. My previous blogs covered some of the following topics: 1. Basics of dynamic...
Posted to
Low Power
(Weblog)
by
Neyaz
on Tue, Oct 5 2010
Simulation of Voltage Scaling for Dynamic Power Reduction
This posting is part of a series of blogs on dynamic power management in digital-centric mixed-signal verification environments. In this post, I'll discuss the simulation of closed-loop voltage scaling for adaptive dynamic voltage and frequency scaling (DVFS). My previous blogs covered some of the...
Posted to
Low Power
(Weblog)
by
Neyaz
on Tue, Sep 7 2010
5 Tips to Help You Finish Your Low Power Design Tapeout On Time
So you're about to start your first low power design. Or second, third, or fourth. As with many tapeouts, you know that with today's tight market windows, most likely the project will go off with a sprinting start (architectural planning), followed by an endurance test (designing and implementing...
Posted to
Low Power
(Weblog)
by
Design4Life
on Fri, Aug 27 2010
Dynamic Power Management – Closed Loop Voltage Scaling
This posting is part of a series of blogs on dynamic power management in digital-centric mixed-signal verification environments. In this post, I'll discuss open-loop and closed-loop voltage scaling. In previous blogs, I covered some of the following topics: Basics of dynamic power management Very...
Posted to
Low Power
(Weblog)
by
Neyaz
on Tue, Aug 24 2010
Power Management for Test: A Means of Addressing False Failures
Engineering teams are tracing test failures back to IR/voltage drop during test mode. These false failures are impacting yield, profitability. We consider this to be a power management issue for test mode and should be approached as early as front-end design and carried through ATPG and pattern/vector...
Posted to
Logic Design
(Weblog)
by
Ed JM
on Thu, Oct 23 2008
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