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System to Silicon Verification – CDNLive Gives a Reality Check on How Hardware and Software Meet
Ever since switching from being a hardware/software chip developer to being an enabler with tools in EDA and embedded software, I was part of a team working towards methodologies and tools to improve the interaction of hardware and software. In December last year -- 15 years in -- I summarized a great...
Posted to
System Design and Verification
(Weblog)
by
fschirrmeister
on Fri, Mar 8 2013
Video: What the Newly Approved IEEE 1801-2013 Low Power Format (UPF 2.1) Includes
The IEEE RevCom (Review Committee) approved a new version of the IEEE 1801 low power format, also known as the Unified Power Format (UPF), March 5. The new version is IEEE 1801-2013 or UPF 2.1. It's a significant step towards "methodology convergence" with the Common Power Format (CPF)...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Mar 6 2013
Video, Presentation – Low Power Design with ARM Physical and Processor IP
Most system-on-chip designers have two things in common - use of ARM physical and/or processor IP, and a mandate to reduce power consumption. There's a wealth of information on low-power design with ARM IP in a newly available video, as well as presentation slides, from an hour-long presentation...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Dec 17 2012
Panelists: Low Power Design Needs System-Level Boost
When low-power design experts get together, much of the conversation turns to the system level. At least that was the case at the recent Low Power Technology Summit held at Cadence Oct. 18, 2012, where audience members questioned panelists about early power estimation, power modeling, and the role of...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Oct 28 2012
Cadence at ARM TechCon – Verification IP, 14nm FinFET, Low Power, Mixed Signal, and More
With nine technical paper presentations, six sponsored sessions, demos, and exhibits, Cadence will have a strong presence at ARM TechCon in Santa Clara, California Oct. 30-Nov. 1, 2012. Cadence papers and sessions will cover topics including advanced-node digital, mixed-signal, low power, verification...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Oct 23 2012
Free Low Power Summit – Dr. Jan Rabaey, ARM, Freescale, and More
If you're involved - or just interested - in any aspect of low-power electronics design, you'll find a lot of good information at a one-day Low-Power Technology Summit at Cadence headquarters in San Jose, California October 18. Highlighting the event is a keynote by Jan Rabaey , professor of...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Sep 24 2012
DAC 2012 Panelists: How to Succeed at 28nm, 20nm and 14nm
What will it take to achieve silicon success at 28nm and below? That was the question put to a panel of experts at a Cadence-sponsored breakfast at the Design Automation Conference ( DAC 2012 ) June 6, where speakers from IBM, Cadence, ARM, Samsung, and GLOBALFOUNDRIES shed new light on business and...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Jun 12 2012
CDNLive! Keynote – New Horizons for ARM Based SoCs
30 billion ARM-based chips have shipped over the last 20 years, but ARM isn't stopping there. ARM is looking beyond cell phones and mobile devices and pursuing new opportunities in the server, home entertainment, and automotive marketplaces, according to Tom Lantzsch (right), executive vice president...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Mar 15 2012
EDA CEOs Speak Out: 3D-ICs, IP Integration, Low Power, and More
What's driving the EDA industry today and where is it headed in the near future? Some high-level answers to these questions came from the EDA Consortium (EDAC) annual CEO Forecast panel Feb. 29, 2012. EDA industry leaders shared their views about 3D-ICs, SoC integration, power management, industry...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Mar 5 2012
ARM TechCon Paper: New Methodology Eases Challenges of 32/28nm Designs
The 32nm and 28nm process nodes, the most advanced nodes currently in production, pose formidable challenges in complexity, power management, variability, and manufacturability. A recent ARM TechCon paper authored by Cadence and Samsung described a methodology that can resolve those challenges. And it's...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Nov 9 2011
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