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low power design

  • Q&A: Qi Wang Updates EDA Power Intent Format Standards

    IC design teams can use one of two formats to express power intent - the Common Power Format (CPF) from the Silicon Integration Initiative ( Si2 ), or IEEE 1801 , also known as the Unified Power Format (UPF). Efforts are now underway to bring the two formats closer together, and Qi Wang, technical marketing...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Mar 20 2013
  • DVCon User Panelists: Is Low Power Design Worth the Costs?

    Much has been written about the specific techniques that IC designers can use for low-power design and verification, but a larger context is missing. What's the end goal, and what are the costs, benefits, and challenges of implementing power management? In a lively panel discussion at the DVCon conference...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Feb 29 2012
  • ARM TechCon Highlights Roundup – Blogs, Videos, and More

    The recent ARM TechCon conference was a great success, and so much happened in 3 days there that it's very difficult to keep track of it all. Here's a "coverage roundup" that includes some pointers to blogs, articles, and videos that might help fill in anything you missed - or shed...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Nov 3 2011
  • RTL Power Estimation

    RTL power estimation is a concept that has existed for a long time. The earlier that you can understand where power is consumed by your chip, the easier it is to make a positive impact. The challenge of course is obtaining accurate estimates. It is easy if you are estimating at the chip-level and most...
    Posted to Logic Design (Weblog) by Jack Erickson on Tue, Sep 8 2009
  • Friday Fun: Adopting New Low-power Design Techniques

    This week's episode has the Dante Semi team employing some new low power design techniques, and using Conformal Low Power to verify their implementation of them. You will also see how the verification team uses low power simulation with Incisive to functionally verify the behavior. It's all going...
    Posted to Logic Design (Weblog) by Jack Erickson on Fri, Aug 21 2009
  • Friday Fun: Modern Methodology Has Benefits

    In this week's episode of "The Next Generation", the Dante Semi team reviews the project status after adopting many new techniques, such as power shutoff, assertion-based verification, physical synthesis, and multi-supply multi-voltage optimization. It looks like things are going well!...
    Posted to Logic Design (Weblog) by Jack Erickson on Fri, Aug 14 2009
  • Don't Let Power Kill Your Project - What % LVT Should I Use?

    By Diego Hammerschlag Sr. Technical Leader Team FED A common question or requirement that designers have is the percentage of low voltage threshold (LVT) cells that should be allowed in a design. For those not familiar with LVT cells, they are special cells that have a lower voltage threshold and can...
    Posted to Logic Design (Weblog) by Team FED on Wed, May 13 2009
  • Leakage Overview and Reduction Techniques

    The Low Power Design Community recently published a nice summary of the techniques folks use to control leakage power, from the process-level to architectural : And our own Steve Carlson is heavily quoted! Actually, one key point I would like to echo is the one about excessive performance margin. We...
    Posted to Logic Design (Weblog) by Jack Erickson on Fri, Apr 17 2009
  • Don't Let Power Kill Your Project

    By Diego Hammerschlag Sr. Technical Leader Team FED Power has gone from an imminent threat to the cause of multiple projects across several vendors going under. I have heard of multiple projects that had working RTL prototypes and were far into the backend flow only to find out that the power used would...
    Posted to Logic Design (Weblog) by Team FED on Tue, Mar 31 2009
  • Design Metrics - ARM is Onto Something

    We here at the Logic Design blog seem fascinated with improving design metrics . Why is that? Perhaps we've seen too many designs go through "long loop" iterations later in the cycle because improper metrics were used to determine the design's "goodness" early in the cycle...
    Posted to Logic Design (Weblog) by Jack Erickson on Mon, Feb 23 2009
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