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A CPF User Perspective on IEEE 1801 (UPF) “Methodology Convergence”
By leveraging Common Power Format (CPF) constructs and removing some older Unified Power Format (UPF) commands, the emerging IEEE 1801-2013 standard (UPF 2.1) will help enable "methodology convergence" with CPF. Kamran Haqqani, principal engineer at Maxim Integrated, will be happy to see this...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, May 13 2013
New Incisive Low-Power Verification for CPF and IEEE 1801 / UPF
On May 7, 2013 Cadence announced a 30% productivity gain in the June 2013 Incisive Enterprise Simulator 13.1 release . Advanced debug visualization, faster turn-around time, and the extension of eight years of low-power verification innovation to IEEE 1801/UPF are the key capabilities in the release...
Posted to
Low Power
(Weblog)
by
Adam Sherilog
on Tue, May 7 2013
Electronic System Level (ESL) Design Gets a Pragmatic Look at EDPS Workshop
Presentations at the Electronic Design Process Symposium (EDPS) April 18, 2013 gave a realistic look at the promises and limitations of electronic system level (ESL) design. Speakers noted that ESL tools are used for the lower levels of the software stack, but typically not for applications development...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Apr 21 2013
CDNLive Silicon Valley 2013 Proceedings Available for Download!
CDNLive Silicon Valley, held March 12-13, 2013, featured nearly 100 technical sessions from customers, partners, and Cadence R&D experts. Presentations from most of those sessions are now available on line . Here's your chance to review presentations you heard, catch up on sessions you missed...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Apr 4 2013
Power Difference between Analog Simulation and RTL complier estimation
Hallo, I am creating a standard cell library. I did analog simulation for cell design and estimated power values for the cells , lets say, NOT, NOR and NAND and I have their power values for static, dynamic, etc. Now based on that I created library file, and used that in RTL omplier for single cell designs...
Posted to
Logic Design
(Forum)
by
GreenGraphene
on Mon, Mar 25 2013
CDNLive High-Performance Track: Do You Have What it Takes to Get Your High-Performance SoC to Market?
Implementing SoCs with embedded processors at advanced nodes has become increasingly difficult. This is due to the complexity of the design functionality as well as the low power and increased performance requirements driven by a plethora of end-user applications in modern hand-held devices. Path-breaking...
Posted to
Digital Implementation
(Weblog)
by
Vasu Madabushi
on Sun, Mar 10 2013
System to Silicon Verification – CDNLive Gives a Reality Check on How Hardware and Software Meet
Ever since switching from being a hardware/software chip developer to being an enabler with tools in EDA and embedded software, I was part of a team working towards methodologies and tools to improve the interaction of hardware and software. In December last year -- 15 years in -- I summarized a great...
Posted to
System Design and Verification
(Weblog)
by
fschirrmeister
on Fri, Mar 8 2013
Video: What the Newly Approved IEEE 1801-2013 Low Power Format (UPF 2.1) Includes
The IEEE RevCom (Review Committee) approved a new version of the IEEE 1801 low power format, also known as the Unified Power Format (UPF), March 5. The new version is IEEE 1801-2013 or UPF 2.1. It's a significant step towards "methodology convergence" with the Common Power Format (CPF)...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Mar 6 2013
Five-Minute Tutorial: Create Encounter Power System (EPS) Power-Grid Views For Standard Cells
In today's tutorial, I'm giving you a sample EPS (Encounter Power System) script that you can use to generate power-grid views for your standard cells. Power-grid views are used during rail analysis, with IR-Drop and EM (electromigration/current density) being the two most popular analysis types...
Posted to
Digital Implementation
(Weblog)
by
Kari
on Fri, Feb 22 2013
Ultra Low Power Benchmarking: Is Apples-to-Apples Feasible?
I noticed some very interesting news last week, widely reported in the technical press, and you can find the source press release here . In a nutshell, the Embedded Microprocessor Benchmark Consortium (EEMBC) has formed a group to look at benchmarks for ultra low power microcontrollers. Initially chaired...
Posted to
Low Power
(Weblog)
by
Pete Hardee
on Tue, Feb 12 2013
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