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low power

28nm
3D-IC
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Managing Inherited Connections with CPF in Virtuoso

Let's assume you are managing a schematic-driven top level design in Virtuoso and you want to import a digital block Verilog netlist into Virtuoso. This is a very common use model in mixed-signal implementation. While the Layout Database is saved in Open Access (OA), the optimized Verilog netlist...

Posted to Mixed-Signal Design (Weblog) by AndreasLenz on Wed, May 23 2012
Free DAC Lunches: Custom/Analog Variability, ARM Low Power Processors in Mixed-Signal Designs

There is such a thing as a free lunch - if you're at the 49th Design Automation Conference (DAC) in San Francisco June 3-7. Cadence is sponsoring two lunches at which you can learn about two important technology topics - custom/analog variability, and the use of ARM processors in low-power, mixed...

Posted to Industry Insights (Weblog) by rgoering on Mon, May 14 2012
Low-Power Design? Brian Bailey Gets It

Hats off to Brian Bailey! If you haven't been following his EDA Designline Power Series on eetimes.com you have been missing out. Throughout April, he's been running a pretty comprehensive series of editorials, opinion pieces and contributed articles on the subject of low power design. As he...

Posted to Low Power (Weblog) by Pete Hardee on Wed, May 2 2012
DVCon 2012 Verification Paper Archive – UVM, Low Power, Mixed Signal and More!

In late April, a wealth of information on IC functional verification became available at the DVCon web site . Both papers and slides are now available for dozens of high-quality presentations given at the DVCon 2012 conference, which was held Feb. 27-March 1, 2012 in Santa Clara, California. You can...

Posted to Industry Insights (Weblog) by rgoering on Tue, May 1 2012
What is Digitally Assisted Analog Design?

Mixed-signal applications are among the fastest growing segments in the electronics and semiconductor industry. Applications in mobile communication, networking, power management, automotive, medical, imaging, safety and security require a very high integration of analog and digital functionality at...

Posted to Mixed-Signal Design (Weblog) by QiWang on Mon, Apr 30 2012
System-Level Low Power Design – What Will it Take to Move There?

While many low-power design techniques are available to IC designers, the greatest potential for power savings is at the system level, where both software and hardware can be considered. So what's standing in the way of system-level low power design, and what needs to happen to make it practical...

Posted to Industry Insights (Weblog) by rgoering on Wed, Apr 18 2012
User View: Going “Green” With Low-Power Design and Clock Concurrent Optimization (CCOpt)

Network processing chips are tough to design. They're big, they're fast, and they have to minimize power consumption. At CDNLive! Silicon Valley 2012 (the Cadence user group conference) Ranjit LoboPrabhu, physical design manager at Netronome Systems , shared some ways his company is going "green"...

Posted to Industry Insights (Weblog) by rgoering on Wed, Apr 4 2012
Where There's Smoke, There's fire in the Belly of an Aspiring Engineer

Humans learn with their hands and, it turns out, electrical engineers are humans. Most of us fondly recall "experiments" we did that made electrical engineering our destiny. But what of the current generation? Have apps deadened the EE in the way video killed the radio star? I am happy to report...

Posted to Low Power (Weblog) by Adam Sherilog on Mon, Apr 2 2012
CDNLive! -- The Other Side of the Low Power Design Techniques

In a recent CDNLive! Silicon Valley presentation titled "Low Power Implementation on the Freescale Kinetis Family," Annis Jarrar from Freescale demonstrated how various low power design techniques were used in the popular Kinetis low power platform. These techniques included power gating with...

Posted to Low Power (Weblog) by QiWang on Thu, Mar 29 2012
CDNLive! Keynote – New Horizons for ARM Based SoCs

30 billion ARM-based chips have shipped over the last 20 years, but ARM isn't stopping there. ARM is looking beyond cell phones and mobile devices and pursuing new opportunities in the server, home entertainment, and automotive marketplaces, according to Tom Lantzsch (right), executive vice president...

Posted to Industry Insights (Weblog) by rgoering on Thu, Mar 15 2012

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low power

Managing Inherited Connections with CPF in Virtuoso

Free DAC Lunches: Custom/Analog Variability, ARM Low Power Processors in Mixed-Signal Designs

Low-Power Design? Brian Bailey Gets It

DVCon 2012 Verification Paper Archive – UVM, Low Power, Mixed Signal and More!

What is Digitally Assisted Analog Design?

System-Level Low Power Design – What Will it Take to Move There?

User View: Going “Green” With Low-Power Design and Clock Concurrent Optimization (CCOpt)

Where There's Smoke, There's fire in the Belly of an Aspiring Engineer

CDNLive! -- The Other Side of the Low Power Design Techniques

CDNLive! Keynote – New Horizons for ARM Based SoCs