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logic synthesis,synthesize RC script

  • How to avoid unwanted removal of logic during synthesis

    Hi All, I am synthesizing a processor design with RTL compiler. The synthesized netlist works fine and contains all necessary logic when I set a loose clock constraint (5000ps). But when I synthesized the same files with a tighter clock constraint (1800- 3000ps) the RTL compiler meets the constraint...
    Posted to Logic Design (Forum) by dkhan on Sun, Jul 7 2013
  • How to use the Encounter RTL Compiler Super-Thread with Tivoli Workload LoadLeveler

    Hello all, Please I would like to use my Encounter RTL Compiler, later the EDI, to place the parallel synthesis into a HPC cluster. I understand that for this purpose I must use Super-Thread, and that I must configure it using: set_attribute super_thread_servers { machine_names } / In this stage I already...
    Posted to Logic Design (Forum) by lvcargnini on Tue, May 14 2013
  • Propagate a clock from .LIB of a block

    Hello all, I am trying to synthesize a module which has a .LIB for one of the blocks. The block has internal clock generators and requires to create a clock on one of the block's ports. I can create the clocks in the top-level by providing hierarchical path. However, I am not able to see the generated...
    Posted to Logic Design (Forum) by randomax on Mon, Apr 30 2012
  • RTL compiler - synthesis

    I am traying to synthesize a design to a library with no basic inverters. In general, RTL compiler requires inverters and some other basic cells. and so i will recieve : "synthesis failed- do not have usable inverters". My library have all the logical veriaty of cells except a straight forward...
    Posted to Logic Design (Forum) by Ivan13 on Sun, Jan 15 2012
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