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logic synthesis,synthesize RC script,Logic Design

  • How to use the Encounter RTL Compiler Super-Thread with Tivoli Workload LoadLeveler

    Hello all, Please I would like to use my Encounter RTL Compiler, later the EDI, to place the parallel synthesis into a HPC cluster. I understand that for this purpose I must use Super-Thread, and that I must configure it using: set_attribute super_thread_servers { machine_names } / In this stage I already...
    Posted to Logic Design (Forum) by lvcargnini on Tue, May 14 2013
  • RTL compiler - synthesis

    I am traying to synthesize a design to a library with no basic inverters. In general, RTL compiler requires inverters and some other basic cells. and so i will recieve : "synthesis failed- do not have usable inverters". My library have all the logical veriaty of cells except a straight forward...
    Posted to Logic Design (Forum) by Ivan13 on Sun, Jan 15 2012
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