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logic synthesis,low power
battery
blog logic design
Borbely
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rc
RTL
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Synthesis
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synthesis RTL Compiler methodology logic design
TeamFED
User View: “Multi-Mode” Synthesis Approach Includes Power Optimization
Logic synthesis is an indispensible IC design tool, but its value has a lot to do with how it's used. At a recent Synthesis Community Event at Cadence Dec. 8, Laszlo Borbely-Bartis, staff design engineer at Micron, described a concurrent multi-mode and low-power optimization synthesis flow using...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Jan 5 2012
How Logic Synthesis is Changing
You probably haven't read much about logic synthesis lately -- it's a mature technology that doesn't attract much attention. But that doesn't mean that new and exciting things aren't happening in synthesis and front-end design, as illustrated by presentations at a Synthesis Community...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Dec 14 2011
8 Users Compare RTL Compiler (RC) vs. Design Compiler (DC) on DeepChip.com
It was refreshing to see what happened when John Cooley made his latest request for reader feedback on his popular DeepChip website catering to the semiconductor design community. A request had come in from a previous DeepChip post prior to the Design Automation Conference (DAC) as follows: Are there...
Posted to
Logic Design
(Weblog)
by
David Stratman
on Mon, Jun 20 2011
DesignWare and AmbitWare Demystified - Why and When to Avoid?
By Diego Hammerschlag Sr. Technical Leader Team FED Most, if not all, synthesis tools today support the use of Synopsys DesignWare or a vendor specific brand of <vendor>Ware such as Ambit's AmbitWare, Cadence's ChipWare and others. I have been frequently asked on the purpose of <vendor>Ware...
Posted to
Logic Design
(Weblog)
by
Team FED
on Fri, Jul 24 2009
RC Design Explorer: Find the Right Balance of Power and Performance
By Paul Weil Sr. Product Engineer You might be aware that RTL Compiler has had the ability to synthesize top-down to multi-supply multi-voltages (MSMV) and optimize across them. Lowering voltage levels can be a great way to reduce switching power, but it comes at the cost of reducing performance. As...
Posted to
Logic Design
(Weblog)
by
Team FED
on Fri, Jul 24 2009
Don't Let Power Kill Your Project - What % LVT Should I Use?
By Diego Hammerschlag Sr. Technical Leader Team FED A common question or requirement that designers have is the percentage of low voltage threshold (LVT) cells that should be allowed in a design. For those not familiar with LVT cells, they are special cells that have a lower voltage threshold and can...
Posted to
Logic Design
(Weblog)
by
Team FED
on Wed, May 13 2009
Blogs: What interests you? What do you want to read about?
With the new blogging opportunities at Cadence, is there anything you'd like to read more about for frontend design? Stuff like: Early chip-planning/prototyping, synthesis (including physical-synthesis), formal verication, DFT, frontend methodologies, etc. My hope is for the blog topics to be informative...
Posted to
Logic Design
(Weblog)
by
Kenneth Chang
on Mon, Sep 15 2008
"What is ChipEstimate?" plus a touch of RC-Physical x 2
Day 2 @ CDNLive San Jose: Another interesting day - met quite a few people, some new, others I met the day before while co-presenting at two morning sessions, and also some of my fav customers. My focus-of-the-day - ChipEstimate awareness with a touch of RC-P. Here are some attendees' feedback: Question...
Posted to
Logic Design
(Weblog)
by
Kenneth Chang
on Thu, Sep 11 2008
Logic Design at CDNLive! Silicon Valley -- see you Sept. 8!
We've been working hard to put together another CDNLive! event, coming up September 8-11 in San Jose. There is a whole track dedicated to Logic Design. Some of the events I'll be working at are: Sept 8. at 8am: Techtorial " Achieve Project Success Through Early Low-Power Planning and Validation"...
Posted to
Logic Design
(Weblog)
by
Jack Erickson
on Wed, Aug 27 2008
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