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logic synthesis,RTl compilerL Compiler

  • How to avoid unwanted removal of logic during synthesis

    Hi All, I am synthesizing a processor design with RTL compiler. The synthesized netlist works fine and contains all necessary logic when I set a loose clock constraint (5000ps). But when I synthesized the same files with a tighter clock constraint (1800- 3000ps) the RTL compiler meets the constraint...
    Posted to Logic Design (Forum) by dkhan on Sun, Jul 7 2013
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