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logic synthesis,FED

Videos, Presentations Highlight Front-End IC Design Methodologies

Want to know how other designers are solving front-end IC design challenges, and what Cadence R&D is doing to help? The Front-End Design (FED) Technology Summit, held at Cadence San Jose headquarters Dec. 6, 2012, provided some helpful answers. Presentations and videos from most of the sessions are...

Posted to Industry Insights (Weblog) by rgoering on Tue, Apr 9 2013
Logic Design and Test Design: Do they need each other?

Cadence has moved from traditional methods and product offerings for silicon test in favor of a new direction, which answers the title question. In 2008, Cadence recognized that while the Encounter Test product had outstanding quality of results, ease-of-use was lacking. What was perhaps most important...

Posted to Logic Design (Weblog) by Ed JM on Sat, Apr 17 2010
DesignWare and AmbitWare Demystified - Why and When to Avoid?

By Diego Hammerschlag Sr. Technical Leader Team FED Most, if not all, synthesis tools today support the use of Synopsys DesignWare or a vendor specific brand of <vendor>Ware such as Ambit's AmbitWare, Cadence's ChipWare and others. I have been frequently asked on the purpose of <vendor>Ware...

Posted to Logic Design (Weblog) by Team FED on Fri, Jul 24 2009
Don't Let Power Kill Your Project - What % LVT Should I Use?

By Diego Hammerschlag Sr. Technical Leader Team FED A common question or requirement that designers have is the percentage of low voltage threshold (LVT) cells that should be allowed in a design. For those not familiar with LVT cells, they are special cells that have a lower voltage threshold and can...

Posted to Logic Design (Weblog) by Team FED on Wed, May 13 2009
Where Oh Where is "number_of_routing_layers"?

OK, I'll just do " set_attribute number_of_routing_layers 6 "... Error : The attribute is read-only. [TUI-26] [set_attribute] : attribute: 'number_of_routing_layers', object type: 'root' : Cannot set or reset read-only attributes. Hey, wait a minute! If you are faced with...

Posted to Logic Design (Weblog) by mrardon on Wed, Mar 18 2009

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logic synthesis,FED

Videos, Presentations Highlight Front-End IC Design Methodologies

Logic Design and Test Design: Do they need each other?

DesignWare and AmbitWare Demystified - Why and When to Avoid?

Don't Let Power Kill Your Project - What % LVT Should I Use?

Where Oh Where is "number_of_routing_layers"?