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lithography,signoff

  • ARM TechCon: Inside Story of a 14nm FinFET Tapeout

    The next frontier in semiconductor design is the 14nm process node, and it will come with a new type of transistor, the FinFET. 14nm FinFET technology moved closer to reality at the ARM TechCon conference Oct. 30, 2012, where a Cadence sponsored technical session announced a 14nm test chip tapeout using...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Oct 31 2012
  • Whitepaper: 20nm is More Than Just Double Patterning

    Probably the most discussed challenge of the 20nm process node is double patterning, which uses extra masks in order to get lithography equipment to print correctly. That is, indeed, a major change that has impacts throughout the design flow. But as a newly published Cadence whitepaper points out, double...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Jul 9 2012
  • “In Design” DFM Signoff – the Inside Story

    As noted in a recent customer announcement with Fujitsu, Cadence offers "in design" design for manufacturability (DFM) signoff for digital, mixed-signal and custom IC design. The basic idea is simple - engineers run signoff DFM checks during the physical design process, instead of waiting until...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Oct 5 2011
  • ISQED Keynote: DFM Heads in Two New Directions

    Design for manufacturability (DFM) is a fairly mature discipline that you don't hear much about these days. But a recent keynote speech outlined two interesting new developments. One new twist complements traditional model-based and rules-based approaches with pattern matching, while another brings...
    Posted to Industry Insights (Weblog) by rgoering on Tue, Mar 15 2011
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