Log In
|
Register
|
Resource Library
|
Worldwide
Asia-Pacific
|
China
|
EMEA
|
India
|
Israel
|
Japan
|
Korea
|
Taiwan
|
Global Office Locator
Solutions
Products
Services
Support & Training
Alliances
Community
About Cadence
Solutions:
Design IP
Mixed-Signal
Low-Power
Advanced Node
Enterprise Verification
Hosted Design
System Development Suite
Solutions Home
Products for:
System Design and Verification
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Manufacturability Signoff
More Products
OrCAD Products
Design IP
Verification IP
IP Catalog
Products A-Z
Products Home
Capabilities and Practices
Methodology Services
Design Services
DFM Services
Educational Services
Programs
SOI Design Hub
Services Home
Support
Support Offerings
Support Process
Cadence Online Support
Software Downloads
Computing Platform Support
University Software Program
Training
Training Options
Training Course Catalogs
Support & Training Home
Programs and Initiatives
System Realization Alliance
Foundry Program
IP Alliances
ChipEstimate.com - Chip Planning Portal
Connections Program
Verification Alliance Program
Channel Partner (VARs) Program
Power Forward Initiative
Standards and Languages
PCB Service Bureaus
Industry Memberships
Alliances Home
Communities
Industry Insights Blog
Low Power Blog
Mixed-Signal Design Blog
System Design and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Quicklinks
All Blogs
All Forums
Community Search
CDN
Live!
User Conferences
Community Home
EDA Vision
Visit the EDA360 microsite
News and Events:
Newsroom
Events and Webinars
Resources:
Customer Success
Newsletters
Publications
Multimedia Center
Logos
Company Info:
Investor Relations
Executive Team
Careers
Contact Us
About Cadence Home
Home
>
Community
>
Tags
> lithography
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.
Register
|
Membership benefits
Get email delivery of the Cadence blog (individual posts).
Industry Insights
Low Power
Mixed-Signal Design
System Design
and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Manufacturability Signoff
All Blog Categories
Popular Tags
Allegro
analog
ARM
Custom IC Design
Digital Implementation
Digital Implementation
e
EDA360
encounter
ESL
ESL
Incisive
IP
Logic Design
Low power
PCB
PCB design
Specman
System Design and Verification
SystemC
SystemVerilog
TLM
UVM
verification
Virtuoso
Browse All Tags
Share
Email
Social Web
*
Required Fields
Recipients email
*
(separate multiple addresses with commas)
Your name
*
Your email
*
Message
*
Send yourself a copy
Subscribe
RSS
Cadence RSS Feeds
Cadence Press Releases
System Design and Verification Blog
Functional Verification Blog
Digital Implementation Blog
Custom IC Design Blog
RF Design Blog
PCB Design Blog
IC Packaging and SiP Design Blog
Manufacturability Signoff Blog
All Blogs
System Design and Verification Forum
Functional Verification Forum
Digital Implementation Forum
Custom IC Design Forum
Custom IC SKILL Forum
Logic Design Forum
RF Design Forum
PCB Design Forum
PCB SKILL Forum
IC Packaging and SiP Design Forum
Manufacturability Signoff Forum
Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.
Contact Us
Cadence Contacts
Community Relations
Customer Support
Employment
Investor Relations
Media Relations
Training
Global Office Locator
Find Offices worldwide
»
Sales Inquiry
Request for Product information
»
Cadence Channel Partners
»
Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234
*
Required Fields
First Name
*
Last Name
*
Email
*
Company / Institution
*
Comments:
*
Send Yourself A Copy
lithography
20 nm
20nm
20nm whitepaper
22nm
28nm
32nm
3D IC
3D-IC
40nm
45nm
A7L
advanced node
advanced nodes
ARM
Cadence
clock concurrent optimization
cloud
cloud computing
CMP
common platform
common platform forum
computational lithography
context
corners
CPF
D2S
DAC
DAC 2011
Deokar
Design
Design Automation Conference
design for manufacturability
design rules
DF
DFM
DFM Coalition
DFM services
DFMC
digital
Digital Implementation
Direct to Silicon
Double Patterning
double patterning aware
DRC
DRC Plus
DRC+
EDI
encounter
EUV
Global Foundries
GlobalFoundries
HKMG
hot spots
hotspot
IBM
in-design
in-design signoff
Industry Insights
IP
layout dependent effects
layout-dependent effects
LDE
LEA
litho
low power
manufacturability
manufacturing
Mixed-Signal
Model-Based DFM
NanoRoute
OPC
pattern matching
placement
routing
SADP
Samsung
Si2
Si2 conference
sidewall image transfer
signoff
silicon realization
smartphones
SMO
SoC
SOI
source mask optimization
SPIE
SPIE 2012
SPIE papers
stmicroelectronics
stress
SystemC
two-color mapping
unified digital flow
variability
variation
VCAD
verification
Virtuoso
yield
CDNLive! – IBM Expert Quantifies Design Impact of Double Patterning
Double patterning will be an essential lithographic technique for ICs at 20nm and below. The more we can understand it, and quantify its impacts on the design flow, the easier it will be to adopt. A good step towards that understanding was taken at CDNLive! Silicon Valley 2012 (the recent Cadence user...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Apr 1 2012
Customer, Partner DFM Concerns Spur New Methodologies
Design for manufacturing (DFM) may not be as "hot" a topic as it was a few years ago - when there were many independent DFM companies - but foundries and chip design companies are in fact very concerned about DFM at 28nm and below. Some of those concerns have given rise to new technologies...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Feb 7 2012
SPIE Papers Showcase DFM and Lithography R&D
Ten Cadence papers planned for the upcoming SPIE Advanced Lithography conference, set for Feb. 12-16 in San Jose, California, demonstrate recent R&D developments in both "design side" design for manufacturing (DFM) and the computational lithography that takes place during the manufacturing...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Jan 26 2012
ARM TechCon Paper: New Methodology Eases Challenges of 32/28nm Designs
The 32nm and 28nm process nodes, the most advanced nodes currently in production, pose formidable challenges in complexity, power management, variability, and manufacturability. A recent ARM TechCon paper authored by Cadence and Samsung described a methodology that can resolve those challenges. And it's...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Nov 9 2011
GLOBALFOUNDRIES DRC+ Donation: New Era for DFM Standards?
DRC+, a pattern-matching design for manufacturability (DFM) technique developed by GLOBALFOUNDRIES in collaboration with Cadence, is heading for standardization through the Silicon Integration Initiative (Si2). As announced Oct. 20 at the Si2 Conference , GLOBALFOUNDRIES has donated DRC+ data structures...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Oct 23 2011
“In Design” DFM Signoff – the Inside Story
As noted in a recent customer announcement with Fujitsu, Cadence offers "in design" design for manufacturability (DFM) signoff for digital, mixed-signal and custom IC design. The basic idea is simple - engineers run signoff DFM checks during the physical design process, instead of waiting until...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Oct 5 2011
Q&A: A Look at 20nm Design Challenges and Solutions
The 20nm process node promises tremendous advantages in power, performance and design capacity, but also raises tough design challenges. These challenges include increased timing and power variability, complex layout rules, and incredibly large designs with massive amounts of IP. A major new challenge...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Sep 11 2011
GTC Presentation: Cadence Outlines Comprehensive 20nm Design Flow
The design and manufacturing challenges of 20nm ICs are formidable, and will not be solved by loose collections of point tools. At the recent Global Technology Conference ( GTC ), Cadence presented its view of 20nm challenges and previewed a comprehensive 20nm design methodology that encompasses custom...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Sep 7 2011
Whitepaper Summary: How to Succeed at 20nm
The upcoming 20nm process node promises tremendous advantages in power, performance and area - but it's also very challenging in terms of design complexity, lithography, and manufacturability. A newly published whitepaper from Cadence, summarized here, sets forth an approach that can mitigate the...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Aug 25 2011
Video: Easing the Design Challenges of Double Patterning at 20nm
Double patterning lithography will be essential at 20nm and below until at least 2014, according to Lars Liebman, distinguished engineer at IBM. But it need not be a huge burden for engineers. In a talk at the Cadence booth at the Design Automation Conference in June, and newly available in the video...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Aug 23 2011
Page 1 of 3 (23 items) 1
2
3
Next >