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GLOBALFOUNDRIES at CDNLive: Why 10nm Requires Design Technology Co-Optimization
It's not too early to start thinking about the 10nm process node and beyond - but such advanced process nodes will require a significant change in the semiconductor design ecosystem, according to Jongwook Kye, fellow for lithography modeling and architecture at GLOBALFOUNDRIES. At the recent CDNLive...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Apr 29 2013
Common Platform Forum Keynotes: 14nm FinFETs and Beyond
How far can we continue to scale semiconductors? 14nm FinFET technology is the next major move, but that's far from the end of the story, according to keynote speakers at the Common Platform Technology Forum in Santa Clara, California Feb. 5, 2013. The keynotes, still available for on-line viewing...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Feb 6 2013
Customer, Partner DFM Concerns Spur New Methodologies
Design for manufacturing (DFM) may not be as "hot" a topic as it was a few years ago - when there were many independent DFM companies - but foundries and chip design companies are in fact very concerned about DFM at 28nm and below. Some of those concerns have given rise to new technologies...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Feb 7 2012
GLOBALFOUNDRIES DRC+ Donation: New Era for DFM Standards?
DRC+, a pattern-matching design for manufacturability (DFM) technique developed by GLOBALFOUNDRIES in collaboration with Cadence, is heading for standardization through the Silicon Integration Initiative (Si2). As announced Oct. 20 at the Si2 Conference , GLOBALFOUNDRIES has donated DRC+ data structures...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Oct 23 2011
“In Design” DFM Signoff – the Inside Story
As noted in a recent customer announcement with Fujitsu, Cadence offers "in design" design for manufacturability (DFM) signoff for digital, mixed-signal and custom IC design. The basic idea is simple - engineers run signoff DFM checks during the physical design process, instead of waiting until...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Oct 5 2011
GTC Presentation: Cadence Outlines Comprehensive 20nm Design Flow
The design and manufacturing challenges of 20nm ICs are formidable, and will not be solved by loose collections of point tools. At the recent Global Technology Conference ( GTC ), Cadence presented its view of 20nm challenges and previewed a comprehensive 20nm design methodology that encompasses custom...
Posted to
Industry Insights
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by
rgoering
on Wed, Sep 7 2011
Common Platform Forum: A Clearer Path to Advanced Process Nodes
Insights into what you can expect at 32/28nm and below came to the forefront at the Common Platform Technology Forum Jan. 18, a well-attended one-day event in Silicon Valley. One point that caught my attention is that IBM is turning to a "gate last" high-k metal gate (HKMG) technology at 20nm...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Jan 18 2011
How DRC Plus Makes DFM Easy at 28nm
Design for manufacturability (DFM) requirements have been a barrier for many design teams who are thinking about moving to lower process nodes. But can DFM actually get easier as process nodes shrink? That possibility is offered by DRC Plus (DRC+), a new technology developed by GLOBALFOUNDRIES in collaboration...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Oct 25 2010
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