Log In
|
Register
|
Resource Library
|
Worldwide
Asia-Pacific
|
China
|
EMEA
|
India
|
Israel
|
Japan
|
Korea
|
Taiwan
|
Global Office Locator
Solutions
Products
Services
Support & Training
Alliances
Community
About Cadence
Solutions:
Design IP
Mixed-Signal
Low-Power
Advanced Node
3D-IC
Enterprise Verification
Hosted Design
System Development Suite
Solutions Home
Products for:
System Design and Verification
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
More Products
OrCAD Products
Sigrity Technologies
Design IP
Verification IP
IP Catalog
Products A-Z
Products Home
Capabilities and Practices
Methodology Services
Design Services
DFM Services
Educational Services
Programs
SOI Design Hub
Services Home
Support
Support Offerings
Support Process
Cadence Online Support
Software Downloads
Computing Platform Support
University Software Program
Training
Training Options
Training Course Catalogs
Support & Training Home
Programs and Initiatives
System Realization Alliance
Foundry Program
ChipEstimate.com - Chip Planning Portal
Connections Program
Verification Alliance Program
Channel Partner (VARs) Program
Power Forward Initiative
Standards and Languages
PCB Service Bureaus
Industry Memberships
Alliances Home
Communities
Industry Insights Blog
Low Power Blog
Mixed-Signal Design Blog
System Design and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
Quicklinks
All Blogs
All Forums
Community Search
CDNLive User Conferences
Community Home
EDA Vision
Visit the EDA360 microsite
News and Events:
Newsroom
Events and Webinars
Resources:
Customer Success
Newsletters
Publications
Multimedia Center
Logos
Company Info:
Investor Relations
Executive Team
Careers
Contact Us
About Cadence Home
Home
>
Community
>
Tags
> linux
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.
Register
|
Membership benefits
Get email delivery of the Cadence blog (individual posts).
Industry Insights
Low Power
Mixed-Signal Design
System Design
and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
All Blog Categories
Popular Tags
Allegro
Analog
ARM
cadence
DAC
Digital Implementation
e
EDA360
encounter
ESL
functional verification
Incisive
industry insights
Low power
Mixed-Signal
OVM
PCB
PCB design
Specman
System Design and Verification
SystemC
TLM
UVM
verification
Virtuoso
Browse All Tags
Email
*
Required Fields
Recipients email
*
(separate multiple addresses with commas)
Your name
*
Your email
*
Message
*
Send yourself a copy
Share
Twitter
Facebook
LinkedIn
Google+
Subscribe
RSS
Cadence RSS Feeds
Cadence Press Releases
System Design and Verification Blog
Functional Verification Blog
Digital Implementation Blog
Custom IC Design Blog
RF Design Blog
PCB Design Blog
IC Packaging and SiP Design Blog
Manufacturability Signoff Blog
All Blogs
System Design and Verification Forum
Functional Verification Forum
Digital Implementation Forum
Custom IC Design Forum
Custom IC SKILL Forum
Logic Design Forum
RF Design Forum
PCB Design Forum
PCB SKILL Forum
IC Packaging and SiP Design Forum
Manufacturability Signoff Forum
Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.
Contact Us
Cadence Contacts
Community Relations
Customer Support
Employment
Investor Relations
Media Relations
Training
Global Office Locator
Find Offices worldwide
»
Sales Inquiry
Request for Product information
»
Cadence Channel Partners
»
Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234
*
Required Fields
First Name
*
Last Name
*
Email
*
Company / Institution
*
Comments:
*
Send Yourself A Copy
linux
16.2
16.3
Allegro IDF EMN MCAD PTC PRO-E
Allegro PCb
Allegro PCB Editor
Allegro PCB SI
Analog
Andrews
android
ARM
ARM Architecture
ARM Techcon
boot loader
booting Linux
busy box
Cadence
connectivity
Constraint Manager
Constraints
Cortex-A
Cortex-A9
data
debug
debugging
embedded
Embedded Linux
embedded software
errata
ESL
Exceed on Demand
Exceed OnDemand
extensible
File System
flexlm
format symbols
FPGA
Free Physical Viewer Contraints Manager
free viewer
Front-end PCB design
funckeys
GDB
GLIBC_2.4
global warming
graphics
Hardware/software co-verification
HDI
height
hi all
Hierarchical
HSPICE
Hummingbird
IC616
Imperas
Incisive
Industry Insights
installation
Installation & Uses
installscape
IP
IP stack
ip-xact
ISX
IT
Jason Andrews
Jim Ready
jumper board
kernel
kernel messaging system
linaro
programmer's guide
QEMU
ring buffer
simulation
SoC
software
software development
System Design and Verification
System Design and Verifcation
System Design and Verification
SystemC
TLM
UART
Ubuntu
uncompressing Linux
unix
VAP
Virtual Machine
virtual platform
virtual platforms
virtual prototoypes
virtual prototype
virtual prototypes
Virtual System Platform
VSP
Windows
Xilinx
Zynq
Zynq virtual platform
Zynq-7000
Zynq-7000'
Embedded World 2013: Virtual Platforms Connected to Everything
Sometimes it is hard to explain why certain ideas take off and why others don’t. There are many stories of poor products that are more successful than much better products. There are also many stories about products that struggle in one time or place, but the same thing is a big hit at another...
Posted to
System Design and Verification
(Weblog)
by
jasona
on Fri, Feb 22 2013
A Concrete Linux Virtual Platform Example
Virtual platforms are used to find many different types of system and software issues. Of course, platforms take some time to develop and debug (regardless of what you read in marketing brochures), but in most situations the benefits outweigh the time and effort required for platform creation. Generally...
Posted to
System Design and Verification
(Weblog)
by
jasona
on Fri, Jan 25 2013
Update to the Linux Kernel Message System
A few months ago I wrote an Introduction to the Linux Kernel Message System . As with all software, especially Linux, things get out of date and need updating. The Linux 3.5 kernel contained changes to the kernel message system that are relevant to my previous article. I found coverage of the changes...
Posted to
System Design and Verification
(Weblog)
by
jasona
on Fri, Dec 7 2012
Creating Custom File Systems and the Linux Loop Device
A few weeks ago we had a crisis at our house. My son managed to delete the data from my daughter's USB memory stick. Not only did he delete it, but he did it in such a strange way I have no idea what he could have done. She was not too happy since all of her recent school work was on the memory stick...
Posted to
System Design and Verification
(Weblog)
by
jasona
on Mon, Nov 5 2012
Ubuntu 12.10 on a Virtual Platform at ARM Techcon
Next week (Oct. 30-Nov. 1) ARM TechCon 2012 is at the Santa Clara Convention Center. As always, Cadence will be at the conference and exhibit, but I would like to especially recommend one paper for people interested in embedded Linux and Virtual Platforms. The presentation is Analysis of Software-Driven...
Posted to
System Design and Verification
(Weblog)
by
jasona
on Thu, Oct 25 2012
Introduction to the Linux Kernel Message System
One of the most common problem reports related to Virtual Platforms running Linux goes something like: I run the simulation and the terminal says "Uncompressing Linux... done, booting the kernel" and nothing happens. One of my favorite books is Embedded Linux Primer: A Practical Real-World...
Posted to
System Design and Verification
(Weblog)
by
jasona
on Tue, Sep 4 2012
Q&A: Jim Ready Discusses EDA Connection to Embedded Software Development
Few people know the embedded OS and software development tool market as well as Jim Ready - after all, he played a key role in its formation. At Ready Systems in 1981, he developed VRTX, the first commercially viable real-time operating system (RTOS). In 1999, as founder of MontaVista Software, he pioneered...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Jul 16 2012
SystemC TLM-2.0 Virtual Platform Direct Memory Interface (DMI) Performance Impact
One of the most interesting concepts in SystemC TLM-2.0 is the concept of Direct Memory Interface (DMI). I remember when Mentor Graphics introduced Seamless back in the mid-1990's. Many users were impressed with how fast it could run embedded software. Of course, things have changed a lot in the...
Posted to
System Design and Verification
(Weblog)
by
jasona
on Fri, Jun 29 2012
Using Physical USB Devices with the Xilinx Zynq-7000 Virtual Platform
There are two choices for how to handle USB devices in a virtual platform. A USB device can be modeled using C/C++ programming, or a physical USB device can be plugged into a computer and attached to the simulator. The Xilinx QEMU for Zynq uses physical USB devices. The Cadence SystemC Virtual Platform...
Posted to
System Design and Verification
(Weblog)
by
jasona
on Thu, May 24 2012
Xilinx Zynq-7000 Virtual Platform Performance: Native Linux vs. VirtualBox
In my last blog post , I covered three frequently asked questions about using the Xilinx Zynq-7000 Virtual Platform as a VirtualBox appliance. Today, I'll cover the next most frequently asked question. It is related to simulation performance. This should not be considered an official benchmark as...
Posted to
System Design and Verification
(Weblog)
by
jasona
on Mon, May 7 2012
Page 1 of 4 (36 items) 1
2
3
4
Next >