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library

  • PART TABLE FILE CHANGES
    For Part Table Files with large amount of package types (i.e. res & caps), when a value is changed or a part is added, regardless if the part is in a project, HDL is notifying and forcing the user to update their schematic when these parts are not even used in their given design. This adds a lot...
    Posted to PCB Design (Forum) by Jonah Stephenson on Thu, Aug 19 2010

  • What's Good About Deleting Parts in ADW? You Can Easily Do This In ADW16.3!
    Part, Schematic, Footprint and Models can all be deleted from the database now with the Allegro Design Workbench ADW16.3 release. Schematic and footprint models may only be deleted if they are not associated with a part. Once a Schematic or Footprint model is deleted from the database, the model is removed...
    Posted to PCB Design (Weblog) by Jerry GenPart on Wed, Aug 18 2010

  • Model Libraries
    I am trying to simulate a simple inverter using nmos, and pmos in Analog_Parts library but the netlist doesn't get created because of the model libraries, both of these transistors have only 3 legs, is there a .scs file to add or a different type of model libraries, where can I find such a file?
    Posted to Logic Design (Forum) by Musmar on Wed, Jun 30 2010

  • RTL Compiler synthesis problem, memory ports not mapped!!! Generated memory macrocells unusable!!!
    Hello, I am facing a problem during the synthesis (RTL Compiler) which I cannot solve. Here is the problem: Initial status: 1) I have coded my digital design in VHDL. 2) The code has been simulated successfully. 3) In my digital design I also need SRAM and ROM macrocells. a. So I used the ARTISAN memory...
    Posted to Logic Design (Forum) by albares on Wed, Jun 30 2010

  • Heterogeneous and homogeneous library part issue
    I have created some heterogeneous and homogeneous parts in my library. I thought I followed the steps it supoosed to be. However, when adding the pars into my schemaitc, I have to end mode, start to add part again and chose the packaging B, C or D to get the correct designator. Otherwise the designator...
    Posted to Logic Design (Forum) by Jennie on Wed, May 26 2010

  • PDK vs. Standard Cell Library
    Hello, I have a question regarding the differences between a PDK/CDK (Process/Cadence Design Kit) and a standard cell library. Sometime people use them interchangeably, but I think there are some inherent differences between these two things. Can anyone clarify this? The reason I asked this question...
    Posted to Custom IC Design (Forum) by weiz on Mon, Mar 30 2009

  • Change the threshold voltage ??
    Hi, I am a student working towards my Master's degree. I am currently doing a project where I have to design a low power circuit. The design consists of multi-Vt nmos and pmos. Can anybody help me out with this? How can I model a high Vt or low Vt transitor in Virtuoso. Although these cells are not...
    Posted to Custom IC Design (Forum) by kgulur on Fri, Sep 26 2008

  • Creating new library in Virtuoso IC60
    hi I have problem in creating new library from library manager in Virtuoso IC60. It shows the following error " *Error* eval: undefined function - libManCreateLib <<< Stack Trace >>> libManCreateLib("cdkCreateNewLib" "" "" "" ""...
    Posted to Custom IC Design (Forum) by ashraf on Thu, Jul 24 2008
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